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Visitor jbarney
Registered: ‎03-21-2019

Zynq VIP register write support

When do you plan on adding support to write to register space in the Zynq VIP?  I want to write to GPIO EMIO register space and the current version of the Zynq VIP doesn't allow this.  Is there a way around it?

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Xilinx Employee
Xilinx Employee
Registered: ‎01-09-2019

Re: Zynq VIP register write support

Hello @jbarney 

Xilinx does not publish timelines or future plans for supported features.

I will say that we do allow you to write to registers using the Zynq VIP to IP in the PL.  This is a supported feature even in Zynq 7000, and can be seen demonstrated in multiple example designs such as the CDMA example design : https://www.xilinx.com/support/answers/50826.html

What is requiring the use of the PS GPIO EMIO as opposed to the AXI GPIO block?  Or could you use the AXI GPIO IP in simulation and then transfer to the PS GPIO EMIO once in hardware?

For future reference this probably would be better suited for the Embedded Processor System Design forum as this question is about the PS VIP and GPIO EMIO.

Don’t forget to reply, kudo, and accept as solution.
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