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Explorer
Explorer
9,431 Views
Registered: ‎07-30-2009

axi dma cyclic mode question

currently i'm using

XAxiDma_SelectCyclicMode function

to setup the cyclic mode.

my understand is once its setup, it will run the same dma transfer indefinitely without input from cpu/app?  however, i try it on the sg_simple_poll example, it seem it only run once.  any idea how to set the dma up, so its running teh same transfer repeatly without cpu input?

 

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11 Replies
Xilinx Employee
Xilinx Employee
9,414 Views
Registered: ‎08-02-2011

Re: axi dma cyclic mode question

Did you set the tail descriptor's 'Next Descriptor' field to point back to the first descriptor?
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Explorer
Explorer
9,403 Views
Registered: ‎07-30-2009

Re: axi dma cyclic mode question

i only has one descriptor, also cyclic mode can only be use in SG?

 

so address 0 for SG engine is point to it self

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Xilinx Employee
Xilinx Employee
9,399 Views
Registered: ‎08-02-2011

Re: axi dma cyclic mode question

i only has one descriptor

Well what's the 'Next Descriptor' field set to for that one? I'm not sure how well this will work... just thinking it through in my head, funny things might happen when the DMA engine tries to fetch the same descriptor from memory once it's done with its local copy. Which happens to be the same thing haha. I think something will be stale and there will be contention.

 

Try with 2 descriptors.

 

also cyclic mode can only be use in SG?

Yes. Cyclic only works in SG mode.

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Explorer
Explorer
9,359 Views
Registered: ‎07-30-2009

Re: axi dma cyclic mode question

so the TX/RX BD space has 0xFFF(sg_sample_poll.c example), base on this the BD calculate quite few BD descriptor.

the BD descriptor are store in BRAM has base address of 0x80000000, which contain next BD ptr at 0x80000040, so on to FC0, at which store/point back to 0x80000000.

 

I use selectcyclicmode function to enable both s2mm/mm2s.  then

Xil_Out32(0x40400010,0x00000050)...... etc to write the tail descriptor for s2mm/mm2s, Axi dma base addr=0x40400000

 

however, the design still only run once.  i try to trigger on tlast of mm2s stream, it just waiting to armed.  this is a loopback between mm2s/s2mm

 

 

 

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Xilinx Employee
Xilinx Employee
9,250 Views
Registered: ‎08-02-2011

Re: axi dma cyclic mode question

Hmm, sounds like your setup should be fine.

Can you probe the SG interface and post some screenshots? It'd be interesting to see what happens when it reaches the last descriptor.
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Observer l.sara_tg
Observer
2,509 Views
Registered: ‎09-08-2017

Re: axi dma cyclic mode question

Dear all,

 

I have the same problem with AXI DMA in CYCLIC mode.

 

I have used XAxiDma_SelectCyclicMode function to setup the cyclic mode in both TX and RX direction,

I have set  the Tail Descriptor register with some value which is not a part of the BD chain (in my case 0x40).

 

Now I see on FPGA chipscope that DMA is correctly cycling,  but when the software calls RxCallback at line

 

    BdCount = XAxiDma_BdRingFromHw(RxRingPtr, XAXIDMA_ALL_BDS, &BdPtr);

 

BdCount is different from NULL only during first occurrance, then it is always NULL because RingPtr->HwCnt = 0,

PostCnt = 1024

AllCnt = 1024

 

Why does it happens?

What do I have to  do in order to keep DMA in cyclic mode and to read data ?

 

Looking forward to receiving your help

 

best regards

 

Sara

 

 

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Visitor vlenoir
Visitor
577 Views
Registered: ‎11-27-2018

Re: axi dma cyclic mode question

Hello,

I get exactly the same issue and I found many thread with similar problem but no answers. Does somebody from Xilinx has an idea ?

Best regards,

Vincent

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Xilinx Employee
Xilinx Employee
563 Views
Registered: ‎02-01-2008

Re: axi dma cyclic mode question

If memory serves me correctly, tlast will trigger a completion. Without tlast, the descriptor will continue to be looped upon but the dma will never complete and cause an irq.

I believe the UG for axi_dma touches on the subject. Search for 'tlast'.

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Visitor vlenoir
Visitor
560 Views
Registered: ‎11-27-2018

Re: axi dma cyclic mode question

Hello,

Not read so much about tlast in AXI DMA documentation (PG21), it's mainly about 2-D transfers. In my case I can easily control the block length as the tlast is generated by a counter. Assuming for instance tlast events every 32 kB of data and IRQ threshold set to 2 I get indeed IOC interrupts every 2 transfers and the actual transfer length returned by the completed BD corresponds to those 32 kB, but only for one cycle. Then even if the IOC occurs there is no more completed BD. One solution is to set the BD ring size to the length of the cyclic chain but in that case, starting from the second cycle, the whole chain is returned as completed at every IOC interrupt instead of 2.

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Visitor vlenoir
Visitor
548 Views
Registered: ‎11-27-2018

Re: axi dma cyclic mode question

I've dumped the completed BD in the IOC interrupt callback and as expected the completed bit in the status field in set but therefore I'm wondering how this bit is cleared for the next cycle ? What I'm guessing, which is what I observe, is that once the first cycle is done the DMA SG engine fetch the first completed BD whose completed bit is already set and go directly to the second BD and so on until the new cycle.

XAXIDMA_IRQ_IOC_MASK
bd_count = 5
radio_if_dma_rx_s2mm_done = 5
Dump BD 1C120000:
        Next Bd Ptr: 1C120040
        Buff addr: 18100000
        MCDMA Fields: 0
        VSIZE_STRIDE: 0
        Contrl len: 30D400
        Status: 8C30D400
        APP 0: 0
        APP 1: 0
        APP 2: 0
        APP 3: 0
        APP 4: 0
        SW ID: 18100000
        StsCtrl: 0
        DRE: 4

invalidate CPU1 L1 data cache (3200000 bytes @ 0x18100000)
invalidate CPU1 L1 data cache (3200000 bytes @ 0x1840D400)
invalidate CPU1 L1 data cache (3200000 bytes @ 0x1871A800)
invalidate CPU1 L1 data cache (3200000 bytes @ 0x18A27C00)
invalidate CPU1 L1 data cache (3200000 bytes @ 0x18D35000)
XAXIDMA_IRQ_IOC_MASK
bd_count = 5
radio_if_dma_rx_s2mm_done = 10
Dump BD 1C120140:
        Next Bd Ptr: 1C120180
        Buff addr: 19042400
        MCDMA Fields: 0
        VSIZE_STRIDE: 0
        Contrl len: 30D400
        Status: 8C30D400
        APP 0: 0
        APP 1: 0
        APP 2: 0
        APP 3: 0
        APP 4: 0
        SW ID: 19042400
        StsCtrl: 0
        DRE: 4

invalidate CPU1 L1 data cache (3200000 bytes @ 0x19042400)
invalidate CPU1 L1 data cache (3200000 bytes @ 0x1934F800)
invalidate CPU1 L1 data cache (3200000 bytes @ 0x1965CC00)
invalidate CPU1 L1 data cache (3200000 bytes @ 0x1996A000)
invalidate CPU1 L1 data cache (3200000 bytes @ 0x19C77400)
XAXIDMA_IRQ_IOC_MASK
bd_count = 0
radio_if_dma_rx_s2mm_done = 10
XAXIDMA_IRQ_IOC_MASK
bd_count = 0
radio_if_dma_rx_s2mm_done = 10
XAXIDMA_IRQ_IOC_MASK
bd_count = 0
radio_if_dma_rx_s2mm_done = 10
XAXIDMA_IRQ_IOC_MASK
bd_count = 0
radio_if_dma_rx_s2mm_done = 10
XAXIDMA_IRQ_IOC_MASK
bd_count = 0
radio_if_dma_rx_s2mm_done = 10

 

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Xilinx Employee
Xilinx Employee
508 Views
Registered: ‎01-09-2019

Re: axi dma cyclic mode question

@l.sara_tg

I think your issue and @vlenoir's might be a little different than the original.  This may be a known issue with the example driver.  I gave a way to fix this to @vlenoir in a seperate post, but I wanted to link you to it here.  Forum post:

https://forums.xilinx.com/t5/AXI-Infrastructure/AXI-DMA-SG-Cyclic-mode-BD-ring-size-vs-BD-allocated-number/m-p/938939/highlight/false#M44052

In that post vlenoir gives his fix code (which is almost identical to the code I have used).  I elaborate further on to add that you should only clear the Completed bit when in Cyclic mode (this can be accomplished by a simple 'if (RingPtr -> Cyclic) ...').

Thanks,

Caleb

Thanks,
Caleb
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