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Visitor jangoris1
Visitor
305 Views
Registered: ‎10-24-2017

cascade block design

Hi,

i was wondering if it is posible to cascade and split block designs.

I have a master block design, which has an axi master and an axi interconnect to connect 4 axi slaves.

 

Then i have a subdesign of which i will connect 4 identical instances to this master. I would like to be able to use a block design inside this subdesign with an interconnect of its own. 

 

The subdesign has a uart and gpio, within the subdesign blockdesign i use address editor to assign address 0x00000000 to the uart and 0x00001000 to the GPIO.

 

Then in the master block design i define the addresses as 

Master1: address 0x00000000

Master2: address 0x00010000

...

 

Am i correct to say that now i can address master 0 gpio at 0x00001000 and master2 gpio at 0x00011000 etc .?

 

Thanks in advance

Jan

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Xilinx Employee
Xilinx Employee
264 Views
Registered: ‎07-30-2007

Re: cascade block design

Yes- you should be able to do it. For optimal timing, make sure that each subsystem is a 2^n sized and 2^n aligned address space.
For example, your map might be:
Sub0:
uart:0x0-0x007fff
gpio:0x008000-0x00ffff
sub1:
uart:0x100000-0x107fff
gpio:0x108000-0x10ffff
sub2:
uart:0x200000-0x207fff
gpio:0x208000-0x20ffff
sub3:
uart:0x300000-0x307fff
gpio:0x308000-0x30ffff

This will yield compact address mapping and some room to grow.
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