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Participant j4xia@uwaterloo.ca
Participant
147 Views

how to get concurrent dual channel DMA

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Hello everyone

 

I facing a design challenge related to multiple channels of DMA. I really appreciate if you can point me to the right source of information of IPs.

 

In my application, I need to SIMULTANEOUSly deploy 2 channels of AXI-S bus (each 128bit wide, 333 MHz) going into two ZYNQ full-power domain slave ports. The two channels carriers data from ADCs and DACs and must be written and read from DDR memory at the same time. 

 

At this moment, I used two DMAs, each controlling data flow into one slave port. Then I used software to start DMA transfer. 

 

The issue with this method is that the relative timing difference between two DMAs can DIFFER SO MUCH and are completely out of sync relative to each other. 

 

So is there any DMA ip that allows multi-channel streaming data into multiple slave ports at the same time?

 

Thank you

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Xilinx Employee
Xilinx Employee
88 Views

Re: how to get concurrent dual channel DMA

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Hi j4xia@uwaterloo.ca,

You are probably using the best IPs for the job. However, you need to provide more information about your requirements regarding the timing between your data streams and do a little more analysis about where the bottle necks are in your system. 

 

For example, is the problem that one DMA always wins arbitration going to the slave port while the other loses? Or is the issue that the register writes that set up a DMA transfer take so long you can't keep them synchronized? Maybe there is something about the way you are handling interrupts from the DMA that could be improved to meet your requirements. There are a lot of pieces to consider.

 

You also need to think about what happens at the DDR interface. Even though your AXi DMAs issue memory reads and writes simultaneously, the PS DDR can only service one read or one write at a time. Sure the DDR has a lot more bandwidth than a slave AXI port to the PS, but it doesn't eliminate the fact that some masters will have to wait to get their read data or receive their write responses.

 

Regards,

 

Deanna

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2 Replies
Xilinx Employee
Xilinx Employee
89 Views

Re: how to get concurrent dual channel DMA

Jump to solution

Hi j4xia@uwaterloo.ca,

You are probably using the best IPs for the job. However, you need to provide more information about your requirements regarding the timing between your data streams and do a little more analysis about where the bottle necks are in your system. 

 

For example, is the problem that one DMA always wins arbitration going to the slave port while the other loses? Or is the issue that the register writes that set up a DMA transfer take so long you can't keep them synchronized? Maybe there is something about the way you are handling interrupts from the DMA that could be improved to meet your requirements. There are a lot of pieces to consider.

 

You also need to think about what happens at the DDR interface. Even though your AXi DMAs issue memory reads and writes simultaneously, the PS DDR can only service one read or one write at a time. Sure the DDR has a lot more bandwidth than a slave AXI port to the PS, but it doesn't eliminate the fact that some masters will have to wait to get their read data or receive their write responses.

 

Regards,

 

Deanna

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Participant j4xia@uwaterloo.ca
Participant
68 Views

Re: how to get concurrent dual channel DMA

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Thank you very much for the reply.

 

We eventually solved the sync issue through additional synchronization logic in RTL. Using ZCU102, we are able to attain two synchronization axis port memory access.