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Visitor thamil_bala
Visitor
463 Views
Registered: ‎05-24-2018

issues in using AXI master_burst in vivado 2018.2

  I am willing to write data directly to DDR from PL without using DMA or CDMA , so that data transmission will be in more user contol. based on some references(mohamad sadri's  "creating custom AXI master interfaces part 3 (lesson7)" video lecture) tries to use axi master burst, but many sub modules(reset module, FIFO module, etc) are missing, also libraries included are in un-referenced mode. where i have to find those missing modules, because i can't able to find any other modules in the "xilinx/vivado/2018.2/data/ip/xilinx/axi_master_burst_v2_0/hdl". I searched in web lot, but I can't able to find any proper references. so please, someone help me to overcome this issue, thanks in advance.

 

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Xilinx Employee
Xilinx Employee
374 Views
Registered: ‎10-04-2016

Re: issues in using AXI master_burst in vivado 2018.2

Hi @thamil_bala,

I am not certain how many of the IPs in that video came from Xilinx or if the speaker created custom IPs. Please note that the video was not produced by a Xilinx employee. 

You can refer the IP Catalog in Vivado to see if the provided Xilinx IPs meet your needs. Otherwise, you might need to contact the instructor in the video to see if he has a design repository he can share with you.

Regards,

Deanna

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Visitor thamil_bala
Visitor
309 Views
Registered: ‎05-24-2018

Re: issues in using AXI master_burst in vivado 2018.2

Hi @demarco

  Thanks for your valuable response, the IP mentioned above "AXI Master Burst V2.0" is part of xilinx IPs. the documentation also available in pg162, I have using vivado 2015.4 and 2018.2 where the submodules are missing in latest version only, so why expecting solution from xilinx. however i solved my problem, as i designed my own axi master for data transfer to DDR3.

 

Regards,

thamilmani