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read transaction ID overflow indicated on pcie xdma to MIG

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Voyager
Posts: 292
Registered: ‎06-20-2017
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read transaction ID overflow indicated on pcie xdma to MIG

[ Edited ]

VLA is indicating a read transaction overflow on on a MIG on a xcvu3p-ffvc1517-2-e. I am attempting to read an 8MB block from DDR4 memory from windows 7 application->driver->pice->xdma->AXI ic->mig.   Is there a limit to the number of outstanding transactions for a given ID?  If so, how do I tell the xdma to increment the transaction ID during reads?  Also, where is transaction ID documented in DocNav or at ARM?  I am attempting to read an 8MB block from DMA into a buffer setup up in a windows application.  Ideally, I'd like to be able to transfer 1GB blocks.  However, in the absense of the appropriate levers, what is a safe block size to request.  This is PCIe gen 3 x16 lanes.  It appears with initial testing that only VLA is flagging this as an error.  The test code I am using has not yet detected any errors in the data provided after it is read.  So is this an academic problem, assuming one master (PCIE/xdma) and one slave (MIG)?

 

The block diagram for the relevant parts looks like this:

 

Capture.PNG

 

 

The diagram is here: (I'll also link directly for larger view).hugess.png

 

 

edit: Trying to fix link to large image

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Xilinx Employee
Posts: 654
Registered: ‎07-30-2007

Re: read transaction ID overflow indicated on pcie xdma to MIG

The overflow is only a problem in the Protocol Checker inside the ILA. You should be able to increase the counter in the ILA Protocol Checker settings.

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Xilinx Employee
Posts: 654
Registered: ‎07-30-2007

Re: read transaction ID overflow indicated on pcie xdma to MIG

The overflow is only a problem in the Protocol Checker inside the ILA. You should be able to increase the counter in the ILA Protocol Checker settings.