UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Voyager
Voyager
291 Views
Registered: ‎06-20-2017

read transaction ID overflow indicated on pcie xdma to MIG

Jump to solution

VLA is indicating a read transaction overflow on on a MIG on a xcvu3p-ffvc1517-2-e. I am attempting to read an 8MB block from DDR4 memory from windows 7 application->driver->pice->xdma->AXI ic->mig.   Is there a limit to the number of outstanding transactions for a given ID?  If so, how do I tell the xdma to increment the transaction ID during reads?  Also, where is transaction ID documented in DocNav or at ARM?  I am attempting to read an 8MB block from DMA into a buffer setup up in a windows application.  Ideally, I'd like to be able to transfer 1GB blocks.  However, in the absense of the appropriate levers, what is a safe block size to request.  This is PCIe gen 3 x16 lanes.  It appears with initial testing that only VLA is flagging this as an error.  The test code I am using has not yet detected any errors in the data provided after it is read.  So is this an academic problem, assuming one master (PCIE/xdma) and one slave (MIG)?

 

The block diagram for the relevant parts looks like this:

 

Capture.PNG

 

 

The diagram is here: (I'll also link directly for larger view).hugess.png

 

 

edit: Trying to fix link to large image

Adaptable Processing coming to an IP address near you.
0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
371 Views
Registered: ‎07-30-2007

Re: read transaction ID overflow indicated on pcie xdma to MIG

Jump to solution
The overflow is only a problem in the Protocol Checker inside the ILA. You should be able to increase the counter in the ILA Protocol Checker settings.
1 Reply
Xilinx Employee
Xilinx Employee
372 Views
Registered: ‎07-30-2007

Re: read transaction ID overflow indicated on pcie xdma to MIG

Jump to solution
The overflow is only a problem in the Protocol Checker inside the ILA. You should be able to increase the counter in the ILA Protocol Checker settings.