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Visitor devarun@18
Visitor
232 Views
Registered: ‎10-12-2018

u-boot not able read address from second AXI master

Hi,

We have two AXI masters in our PL (FPGA). We are able to read and write memory offsets of the first AXI master from u-boot, but reading and writing the memory offsets of the second AXI master, makes the system freeze.

Is there any additonal changes needed in the fsbl or u-boot for the second AXI master.

Thanks and regards,

Dev

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5 Replies
Xilinx Employee
Xilinx Employee
209 Views
Registered: ‎09-14-2018

回复: u-boot not able read address from second AXI master

Hi devarun@18 

Do you mean you have two customed AXI slave IP connected to PS?  And you cannot reach the second IP address both with u-boot and baremetal user application? Could you give more details or just post a screen-shot of your connection in Block design?

 

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Visitor devarun@18
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198 Views
Registered: ‎10-12-2018

回复: u-boot not able read address from second AXI master

Hi Chaoz,

We have created two custom AXI IPs in the FPGA and need to access them through the PS. Below is the configuration we get in the system.hdf

M_AXI_PERIPHERAL_1 : BaseAddress : 0x43C00000 : High Addr 0x43CFFFFF

M_AXI_PERIPHERAL_2 : BaseAddress : 0x43D00000 : High Addr 0x43D00FFF

We are able to access M_AXI_PERIPHERAL_1 throught the u-boot and kernel but cannot access (read or write) M_AXI_PERIPHERAL_2.

M_AXI_PERIPHERAL_1 is AX4 type and M_AXI_PERIPHERAL_2 is off type AX4Lite.

Do we need to make changes in the pl.dtsi for this ? If so could you point to some documentation to achieve this.

 

Regards,

Dev

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Xilinx Employee
Xilinx Employee
189 Views
Registered: ‎09-14-2018

回复: u-boot not able read address from second AXI master

devarun@18 

hi , Is it possible to access to the address with Baremetal? - If it failed with baremetal, it could be that your axi4-lite interface logic violates protocal spec. To further debug, you can watch the AXI signals with ILA.

"Do we need to make changes in the pl.dtsi for this ?" -- I think there is no need , as you are not using any drivers.

 

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Visitor devarun@18
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169 Views
Registered: ‎10-12-2018

回复: u-boot not able read address from second AXI master

Hi Chaoz,

I am able to access the memory location through xsct  basically through baremetal but not through u-boot and kernel.

Is there a configuration I am missing in fpga or fsbl of PS.

Regards,

Devarun

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Xilinx Employee
Xilinx Employee
154 Views
Registered: ‎09-14-2018

回复: u-boot not able read address from second AXI master

devarun@18 

In your design your are connecting two axi ip through a interconnect IP to PS GP port, right?

As I know, there is no need of extra configuration for a second axi IP.

Could you try with a xilinx IP(for example, axi-gpio) on the second port, to see if it can work.

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