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Visitor haitao73
Visitor
294 Views
Registered: ‎11-01-2018

zu7 PS HP port AXI write channel error

Hi,

    I'm migrating our ai accelerator from zynq 7000 to ultrascale+MPSOC, our ai accelerator is at PL side and direct connect to HP 0-3 port of PS side. In zynq 7000, I using AXI3 and limit the read burst num to 25, while using AXI4 in MPSOC, I limit write burst num to 8.

    When I do simulation, i encountered axi vip error, that is "WREADY: Too many outstanding Ready objects pending." I don't know why. I checked the write transfer but nothing found.

TIM截图20181201111347.png

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Xilinx Employee
Xilinx Employee
201 Views
Registered: ‎10-04-2016

Re: zu7 PS HP port AXI write channel error

Hi @haitao73,

Which version of the tools are you using? The MPSoC VIP has a few issues with the slave ports that were resolved in 2018.1.

If you are using 2018.1 or newer tools release, the other thing to check is if you are following the DS941 for how to reset the MPSoC VIP. 

https://www.xilinx.com/support/documentation/ip_documentation/zynq_ultra_ps_e_vip/v1_0/ds941-zynq-ultra-ps-e-vip.pdf#page=10

Regards,

Deanna

 

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