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MicroZed Chronicles: Accelerating IP creation with Model Composer

Xilinx Employee
Xilinx Employee
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This content is republished from the MicroZed Chronicles, with permission from the author and Hackster.io.


There are several different ways in which we can implement our design in programmable logic e.g. RTL, HLS, SDSoC & SDAccel and over the years I have looked at most of these for this blog or my hackster projects.

One method of programmable logic development we have not looked at is Model Composer, which enables a model based design flow. 

306_Fig1.pngModel Composer EcoSystem

If you are not familiar with Model Composer, it is used in conjunction with MathWorks Simulink and provides a library of blocks which are optimized for implementation in programmable logic. This library includes support for a number of applications and functions including Computer Vision, Image processing, Math, Linear Algebra and of course logic functions. 

Just like using IP Integrator in Vivado, Simulink and Model Composer enables us to develop, simulate and verify our algorithms in a graphical environment. 

Once we are happy with the performance of the algorithm in Simulink / Model Composer, we can implement the algorithm in programmable logic. This implementation uses High Level Synthesis with automatic insertion of High Level Synthesis optimizations to obtain the desired performance. 

To show just how easy it can be to get started with using Model Composer and Simulink. MathWorks recently released four videos outlining how Simulink and Model Composer can be used to create a image processing application which detects road signs on a Ultra96.

306_Fig2.pngDetecting the Yellow of a Road Sign

The four videos walk us through the complete project creation in just under 25 Minutes. 

  • Video One — Introduces us to the project, the tools chains used and how to set up the project
  • Video Two — Shows how we can create the algorithm and update simulate performance using live video. Before showing how we can generate the RTL for implementation using HLS.
  • Video Three — Demonstrates how the IP block created in the Matlab Simulink environment, can be imported and used in our Vivado design. 
  • Video Four — Concludes the lab, outlining how the bit file can be generated and used. 

Of course, the output from this video series is an IP block which has been implemented in a Ultra96. To create an application around it as shown in the Simulink Simulation video we would need to be able to interface with both a camera and a display. 

306_Fig3.pngIP Block Ready for Implementation in Vivado

An example of this camera / display solution would be the implementation of the IP block with a MIPI camera input and DisplayPort output on the Ultra96 (see how to use DisplayPort here P1, P2). 

To help demonstrate such an example, I have just purchased a MIPI Interface board for my Ultra96. This board supports a range of MIPI cameras, including R-PI cameras and also provides a DSI output. The board I purchased came with dual OV5640 cameras.  


Using this board we can configure and control the MIPI cameras using I2C located in either the Processing System or the Programmable Logic and capture the camera output using MIPI CSI-2 receivers in the PL. 

Creating this example will take me a little time. However, for now we can see from the videos model composer provides a very easy flow which we can use to create and implement algorithms in our programmable logic design. 

Keep an eye on my hackster.io projects, the MIPI / Display port example will be appearing soon!


See My FPGA / SoC Projects: Adam Taylor on Hackster.io

Get the Code: ATaylorCEngFIET (Adam Taylor)

Access the MicroZed Chronicles Archives with over 300 articles on the FPGA / Zynq / Zynq MpSoC updated weekly at MicroZed Chronicles.