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MicroZed Chronicles: Clock Monitoring

Xilinx Employee
Xilinx Employee
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This content is republished from the MicroZed Chronicles, with permission from the author and Hackster.io.

 

Clocking is really one of the most fundamental aspects of FPGA / Programmable logic design, if we get it wrong then we are in a lot of trouble. Getting it wrong means our design may struggle to meet timing, or worse if we have not followed the clock guidelines regarding pin placement, clock usage, and routing correctly we may even struggle to implement the design. 

Of course this is before we even consider the more complex aspects of clocking which must be addressed such as working with multiple clock domains. 295_Fig1.png

However, once we achieve timing closure and verify all Clock Domain Crossings are safe. For certain applications e.g. control, high reliability, mission / safety critical we still cannot rest. In these applications we may want to understand the quality of the clock in our design at run time, so the results can be used as part of the built in self test (BIST) solution. 

This is where the clock monitoring capability provided by the Clock Wizard come into play. Using clock monitoring we are able to observe

  • If a monitored clock stops 
  • If a monitored clock glitches 
  • If a monitored clocks frequency goes out of range

Enabling clock monitoring in the clock wizard allows us to be able to monitor up to four clocks. These clocks can be either independent and not used by the clock wizard output clock generation or used also for the clock wizard output clock generation. 

We enable the clock monitoring when re-customising the clock wizard IP.

295_Fig2.png

Once the clock monitoring is enabled on the first tab of the re-customise IP dialog, we can select the clock monitoring tab and configure the following 

  • The number of clocks to be monitored
  • The reference clock frequency 
  • The clock tolerance 

The reference clock is the clock used to monitor the four clocks, it is assumed the reference clock is stable and error free. 

295_Fig3.png

If we want to use one of the monitored clocks to generate the output clock we need to use clk_0 or clk_1 and select the PLL/MMCM option in the second column. 

To raise awareness should an error arise on a monitored clock the clock wizard contains a number of discrete outputs. Discrete outputs are provided to indicate Clock_stop, Clock_Glitch and Clock_OutOfTolerance. Each output four bits with the appropriate bit set for the corresponding clock. 

When clock monitoring is enabled the Clock Wizard module also instantiates an AXI Lite interface. This allows a processor or other AXI master to read the clock monitoring status using AXI. 

To help create a more responsive system an interrupt is also provided which can be configured over AXI to issue interrupts should certain clock events occur. 

Being able to monitor the clocks in this system is very useful, we can also use such monitoring for detecting if external clocks are present before taking action. This is especially true if we want to select between different input clocks. 

 

See My FPGA / SoC Projects: Adam Taylor on Hackster.io

Get the Code: ATaylorCEngFIET (Adam Taylor)

Access the MicroZed Chronicles Archives with over 290 articles on the Zynq / Zynq MpSoC updated weekly at MicroZed Chronicles.