Editor’s Note: This content is republished from the MicroZed Chronicles, with permission from the author.
In last week’s blog, we examined how to install and use the open-source simulator GHDL. This week, we will expand the use of GHDL with an open-source verification framework for VHDL called UVVM.
UVVM or Universal VHDL Verification Methodology is a free and open-source verification framework created by the Norwegian company bitvis.
Funded in part by the European Space Agency (ESA), UVVM is one of the most powerful VHDL verification frameworks. Along with the framework for creating the test benches which includes scoreboards, alerts, logging, checking, transactions and more, UVVM also provides several VHDL Verification Components (VVC). These VHDL Verification Components provide users with a fast and easy method to implement standard interfaces like the ones listed below.
General Purpose IO
SPI / I2C
Simple Bus Interface
These VVCs enable the developer to focus on test implementation versus the creation of the infrastructure necessary to perform the tests. Of course, custom VVCs can also be created because the framework is open source.
We will do a deep dive into the UVVM framework and discuss how a UVVM test bench is constructed, but first, we need to install UVVM and compile the UVVM libraries.
First, we are going to clone the UVVM repository from GitHub. However, to ensure we can compile the libraries correctly and run the example projects, we need to ensure we are using the following:
Once the GitHub repository with the correct tag has been cloned or downloaded, the next stage is to compile the libraries and the example application.
Rather helpfully, the UVVM clone comes with two example test benches. The first models an interrupt system while the second implements a UART module using the UVVM framework.
These example designs are highlighted in the diagram below.
You will see a script folder under the bitvis_uart folder. Contained within this folder is everything needed to compile and run the simulation using different simulators. For GHDL, we need to use the ghdl_compile_all_and simulate.sh script.
This script contains everything needed to run the example design and can be used as a basis for verification of custom modules as we later develop them.
Running the example is very straight forward. In Linux, we can run a bash terminal and source the script. In Windows, we can do a similar thing using Git Bash. If Git Bash is installed, this should be available by right clicking in the script area and selecting Git Bash here.
Once Git Bash is open, we can source the script using the command:
This will cause the compilation of UVVM along with the RTL and test benches. The simulation is executed once all the source is finally compiled.
As the simulation runs through to completion, the UVVM transcript will appear in the Git Bash window as the VVC are used to test the UART module.
Once completed, this log will summarize the number of warnings and failures within the test bench.
These logs are also provided in a text format within the directory and can be gathered as evidence to demonstrate the performance of the RTL module and verification.
Now that we know how to use the UVVM framework, next week’s blog we will look at the structure of a UVVM test bench in depth so that we are comfortable creating our own test benches.