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MicroZed Chronicles: MicroZed PYNQ

Xilinx Employee
Xilinx Employee
0 0 339

Editor’s Note: This content is republished from the MicroZed Chronicles, with permission from the author and Hackster.io.

 

I must admit, I have not worked with the board that this series of blogs is named after since I created the Vitis Acceleration Platform. However, in the past week, I have had two clients reach out to me for help regarding controlling and communicating with custom IP they developed in the programmable logic.

This got me thinking that what would help them is a PYNQ image for the MicroZed board. This helps in several ways:

  • PYNQ comes with drivers for most PL peripherals and IP. As such, we can focus on the configuration and behavior of the IP.
  • The PL design will be undergoing changes in development, and PYNQ enables the new overlay to be uploaded and tested with ease.

Of course, to be able to provide this image, I first need to create a PYNQ image for the MicroZed 7020. Doing so is quite straight forward and it is what I am going to demonstrate. To do this, we will need a virtual machine with the latest PYNQ repository cloned. You can see how to do this here.

To create a MicroZed PYNQ image, first I am going to create a Vivado design which configures the processing system. As the MicroZed is a system-on-module with most IO broken out for use on an adapter card, I will not be including much in the programmable logic design. I included an AXI.

347_Fig1.png

In the platform view, I did enable the AXI GP masters and HP slaves along with 15 interrupts from the concat block and the four fabric clocks.

Once this was completed, the bit stream was built and the HDF exported with the bitstream. With a basic hardware configuration, we can now build a PetaLinux BSP. All PYNQ builds are based off a PetaLinux BSP. If you are unfamiliar with PetaLinux, see my introduction blogs here P1, P2, P3, P4.

In PetaLinux we can create a BSP in four simple steps.

  • Create a PetaLinux project with the command – petalinux-create  --type project --template zynq --name mz_7020_pynq
  • Configure the PetaLinux project to reflect the information in the HDF – petalinux-config --get-hw-description <directory of HDF>
  • Build the PetaLinux Embedded Linux OS – petalinux-build
  • Create the necessary boot files – petalinux-package --boot --uboot –fpga
  • Package the project as a BSP – petalinux-package –bsp -p mz_7020_pynq -o mz_7020_pynq.bsp

347_Fig2.png

Once the PetaLinux BSP is available, we can build a PYNQ image by creating a board definition for under the pynq/boards directory. 

347_Fig3.png

Under this directory, place the new PetaLinux BSP and create a specification which contains the following:  

347_Fig4.png

This defines the processor type as 32-bit Arm in addition to the BSP we want to base the build from and the final stage packages to be included.

We can then build the PYNQ image using the command =<boardname> from the sdbuild directory.  Note this might take several hours and make sure you have run the set-up environment script first in the sdbuild/scripts directory.

Once the image is ready it will be available under the outputs directory in sdbuilds.

All we need to do then is flash the image to an SD card, insert it into the MicroZed and boot the board with an internet connection.

You can then open a browser to navigate to \\pynq:9090 and you will see the log in screen for the Jupyter Notebooks.

Now we have a basic PYNQ image. Next we need to check that the image will work OK with custom overlays because that is what we want to help us accelerate verification and testing of custom PL overlays.

To double check this, I created a simple overlay which contained a BRAM mapped into the processor memory map.

34_Fig5.png

Once this bitstream was built, it was uploaded to the MicroZed using the Samba server in PYNQ. Along with the bit file, I also uploaded the following:

  • Bit file – programmable logic design for the PL.
  • Hardware hand off file – defines the description of the hardware design in the PL and connections to PS.
  • Block diagram TCl – not strictly needed but can be used to recreate the design if required in Vivado.
  • Mz_base.py – python file defining the overlay class.
  • __init__.py – initialization file.

Once these files have been uploaded, we can create a simple application to test out the MicroZed PYNQ image with the new overlay. 

347_Fig6.png

With the overlay working as expected, I can now start looking at the more detailed overlays which were causing my clients the issues.

I will share the PYNQ MicroZed overlay if anyone is interested. Just let me know.

 

See My FPGA / SoC Projects: Adam Taylor on Hackster.io

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Access the MicroZed Chronicles Archives with over 300 articles on the FPGA / Zynq / Zynq MpSoC updated weekly at MicroZed Chronicles.