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MicroZed Chronicles: PYNQ Image for Largest FPGA in Zynq UltraScale+ MPSoC Family - TySOM-3A-ZU19EG Development Board

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Xilinx Employee
Xilinx Employee
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Editor’s Note: This content is republished from the MicroZed Chronicles, with permission from the author.

 

We’ve looked at PYNQ and how it enables us to accelerate our initial developments and verification of algorithms several times throughout this blog and Hackster projects. We get this benefit because we can leverage the PYNQ drivers to work with AXI-Lite, DMA, and VDMA interfaces quickly and easily. We can control complex interfaces with just a few lines of Python and are also able to use popular Python packages such as matplotlib and NumPy to generate data for injection into the algorithm in the PL or to post obtained process results.

377_TySoM_Fig1.jpg

Of course, typically PYNQ images have been made available for devices from the low and mid-range portfolio of the Zynq-7000 and Zynq MPSoC UltraScale+ families. Typical devices include the Z-7020 and ZU4EG or ZU7EV. These devices can be used to prototype applications, however, larger applications requiring more programmable logic resource becomes a challenge.

Therefore, I was pleased to see a PYNQ image being released for the TySOM-3A- ZU19EG. This development board contains the largest Zynq UltraScale+ MPSoC EG range of parts enabling the implementation of the most challenging of programmable logic application.

I am a big believer in being able to prototype systems and test algorithms on actual hardware, using the real-world sensors. This enables the performance of the sensor to be assessed in representative real-world conditions, thereby identifying and retiring potential performance issues earlier in the development phase. With its ability to create dashboards and controls via widgets, the PYNQ Jupyter environment also presents a nicer environment for displaying interim results.

It is not just the PYNQ image or the resources available in the ZU19EG MPSoC that enables developers to prototype the system, it’s also the interfacing capabilities of the TySOM-3A development board.    

377_TySoM_Fig2.jpg

With the TySOM-3A we gain access to the following:

  • 8GB DDR4 SODIMM Memory for PS
  • 8GB DDR4 SODIMM Memory for PL
  • 2 Gb NAND Memory   
  • 512Mb QSPI Flash Memory
  • Wi-Fi/Bluetooth Module
  • PCIe x1 GEN3/4
  • HDMI 2.0 Out
  • HDMI 2.0 IN
  • DisplayPort
  • SATA
  • Two FMC Connectors

This enables developers to interface quickly and easily with off-the-shelf FMC or custom FMC connectors that previously provided interfaces to the system being prototyped, while the PL DDR provides the ability to store waveforms or images for stimulating as part of the algorithm test. Of course, the PL DDR can also be used to provide low latency DDR storage as part of the algorithm. Aldec provides a portfolio of FMC HPC daughter cards for applications such as ADAS, networking, data transferring, IoT and more.

As with many PYNQ images, a base reference design is provided with the TySOM-3A and the reference design includes the ability to connect to the HDMI IP/OP and the FMC connectors. 

377_TySoM_Fig3.png

This enables the developer to be able to quickly and easily get up and running using the PYNQ image to interact with the IO sensors, cameras etc.

If needed, the developer can create a new overlay using Vivado. The overlay can be up and running in minutes once the bit file is available provided that all the IP which connects to the processing system uses AXI-based interfaces.

Overall, it is nice to see a PYNQ image for the TySOM-3A that provides a nice development platform to  enable the prototyping of complex algorithms. I think it should be a requirement to have a PYNQ image available for all Zynq-7000 and Zynq UltraScale+ MPSoC boards.