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MicroZed Chronicles: PYNQ, Zynq UltraScale+ RFSoC & SD FEC

Xilinx Employee
Xilinx Employee
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This content is republished from the MicroZed Chronicles, with permission from the author and Hackster.io.

 

A few weeks ago, I attended the Xilinx Worldwide Sales Conference. Besides the opportunity to stay in a hotel where part of the Arnold Schwarzenegger film True Lies was filmed, this was a great opportunity to get hands on with new tools and boards in a number of lab sessions.

307_Fig1.pngZynq UltraScale+ RFSoC ZCU111 Evaluation Kit

One of my favourite labs was the PYNQ RFSoC lab which I thought really demonstrated the RFSoC and its capabilities. This lab outlined not only the RF converter capabilities but also those of the SD FEC and even outlining how python can be used for digital signal processing on the Processing System (PS). Of course, the lab swiftly followed up with how the DSP algorithm could be accelerated using PYNQ and programmable logic overlays.

I was happy to see the inclusion of these labs in the latest PYNQ V2.4.1 release for the ZCU111. So, I thought I would dig out my ZCU111 and rerun the lab and share some of the most interesting results. 

Along with the new RFSoC Overlay and associated notebooks, the RFSoC PYNQ labs also changes how we interact with the Jupyter environment. Instead of using the standard Jupyter interface which we will be familiar with from our previous PYNQ adventures, and is shown below

307_Fig2.pngTraditional Juypter Notebook view

We use the Jupyter Labs interface which we access by adding the /lab address to the standard pynq:9090 (http://pynq:9090/lab). This opens up a range of new features for developing and running our PYNQ applications. 

At first glance Jupyter lab appears much more like a traditional IDE, and includes new features such as the ability to drag and drop cells between notebooks and associate terminals with notebooks for scratch outputs. 

Use of Jupyter labs is not only limited to this set of labs, we can use labs on any PYNQ image by going to Pynq:9090/lab 

307_Fig3.pngJupyter Labs running on the Zynq UltraScale+ RFSoC

Once we have Jupyter labs up and running, under the RFSoC_Workshop folder you will see five notebooks. 

  • Introduction — Basic introduction to working with PYNQ and Jupyter notebooks 
  • PYNQ & Data Converter — QPSK signal generation and reception using the Data Converters under control of the PYNQ framework
  • PYNQ & SDFEC — Low Density Party Check (LDPC) encoding and decoding to demonstrate the ability of the Soft Decision Forward Error Correction Integrated block to demonstrate how the RFSoC can work in noisy environments.
  • DSP and Python — Introduction to DSP with Python 
  • DSP and PYNQ — Introduction to DSP with PYNQ 

For the remainder of the blog we will be examining the PYNQ & Data Converter and PYNQ & SDFEC notebooks. 

To Make use of this notebook on the ZCU111 we need to connect J4 to J5 on the RF FMC breakout board which enables us to loop back the RF Converters. 

The PYNQ overlay once downloaded enables us to, generate QPSK signals in the PL and transmit them via the RF Data Converter as shown in the diagram below. The points marked with dotted lines in the diagram enable us to visualize the waveforms in the Jupyter notebook at points in the processing chain. 307_Fig4.pngQPSK Overlay architecture

For example ol.qpsk_tx_get_symbols() call provides us with information which allows us to generate athe following plot307_Fig5.pngol.qpsk_tx_get_symbols Plot — Click the play arrow for this plot to free run with updates in the Jupyter lab

We can see both the time and frequency domain plots using the get shaped FFT and get shaped time call, these are the signals the RFSoC transmits  

307_Fig6.pngTime domain representations of the transmission


307_Fig7.pngFrequency domain representations of the transmission
Of course, we want to be able to receive the RF signal and decode the data contained within it. Examining the RF Receive path we can see the same ability to observe the signal at various points in the processing chain.

307_Fig8.pngQPSK Receive Path

Here we can look at the decimated time and frequency domain along with a unsynchronized constellation diagram  

307_Fig9.png

 

307_Fig10.png307_Fig11.pngRaw and Decimated, Receive Time and frequency domain along with raw constellation

Once these raw signals have been received, we can synchronize the output data and see the final constellation. 

307_Fig12.pngSynchronized Constellation

The ability to visualize the inspect the different stages of the transmit and receive processing chain is for me very interesting and enables understanding of the RF data converters. Once we have run through these base settings, we can also use the Jupyter notebook to customize the TX and RX chain to explore the impacts of changing NCO frequencies etc. and again observe the effects at different points in the processing chain. 

The second notebook PYNQ & SD FEC enables us to see the performance of the Soft Decision Forward Error Correction block and contains the architecture below. 307_Fig13.pngSD FEC — PYNQ Overlay

One of the great things about this notebook is that it allows us to see the performance of SD FEC for several different modulation schemes and codes. These tests take a few minutes to run but once the completed you can see the performance of the SD FEC across different modulations and LDPC codes.  

307_Fig14.pngCalculating the Modulation

As you can see below the results for the SD FEC across different modulation schemes plot the error vs SNR (dB). For each of the schemes 200, 40 Mb blocks are passed through the SD FEC. 307_Fig15.pngSD FEC Results Plot for different Modulation and Codes

The performance of the SD FEC in the RFSoC example can be correlated against the IP performance specified in the product guide. But you can see the more complex the modulation scheme the more susceptible it is to noise. The SNR also impacts the throughput we can achieve.

Running the SD FEC again using different LDPC codes we can see in the results the system level trade off between throughput and Bit Error Rate. 307_Fig16.pngSDFEC Performance with different LPDC codes

 

One of the final tests in the lab is to report the throughput for a QAM64 modulation scheme. When this is checked against the predicted DOCSIS short performance this is close to the prediction 307_Fig17.png

While this blog has been a whistle stop tour of the RFSoC workshop, hopefully it shows the benefits of using PYNQ with the RFSoC and the capabilities provided by both the RF Converters and the SD FEC. 

You can find out more about the RFSoC workshop at the link below :

Xilinx/PYNQ_RFSOC_Workshop
A collection of designs and notebooks for the PYNQ & RFSoC workshop - part of the ZCU111's v2.4.1 PYNQ image. These…github.com

 

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