Over the last couple of weeks, we have examined how Vivado can help us identify design issues that might impact the implementation.
However, as all engineers know, the earlier we can find an issue, the easier and cheaper it is to correct (both financially and in time spent). What is even better is to avoid the issue in the first place. This is where using Xilinx UltraFast design methodologies can offer significant benefits when implementing designs.
By following the rules outlined below, we can create a design with reduced issues encountered later on. Of course, the UltraFast design methodology rules provide significant insight and explanation as to why the rules exist. However, five of the most critical are summarized below.
Optimize for hierarchical design and implementation using advanced features such as out-of-context synthesis. A optimised hierarchical design will provide the following
Place the I/O buffers at the highest level possible – preferably in the top level.
Ensure clocking functions are implemented at the top level if possible.
Whenever possible, register the inputs and outputs of each hierarchical block.
Control Signals – A control signal consists of set/reset, clock enable, and clock. These control sets drive the logic resource utilisation. A new control set is defined for each unique combination of set/reset, clock enable, and clock signals. Many control sets can impact the resources available because all registers in a slice must have the same control set.
Reset – Using a reset or not, synchronous or asynchronous can impact not only the design’s performance but also area and power. Inside a Xilinx FPGA, synchronous code can be implemented in LUTs, registers, SRLs, BRAM or LUT memory, and DSP48 registers. Use and style of reset use can impact the choice of resource and may lead inadvertently to a sub-optimal implementation. UltraFast rules recommend using resets on control paths but not on data paths. If a reset is required, the UltraFast rules recommend a synchronous reset. Synchronous resets map to more logic resources and provide more flexibility for control path mapping. A special warning to be especially careful when working with arrays though. Resetting the array can lead to mapping to registers and not BRAM resources.
Clock Enables – Clock enables can occur when an incomplete conditional statement is used inside a synchronous process. This can lead to a clock enable being implemented to retain the last value. If the conditional statement is closed (e.g. if-else condition declared) this can reduce the need for a clock enable and reduce the number of control sets required.
When working with RAM and ROM, leverage the Xilinx XPM macros which enable portable solutions which in turn simulate fast and enable considerable optimization of RAM structures for power and performance.
It is worth pointing out that both clock enables and resets can be controlled using a one of the synthesis attributes EXTRACT_RESET/DIRECT_RESET DIRECT_ENABLE and EXTRACT_ENABLE. These attributes enable control set mapping to be direct to pins or via a logic cone.
The best way to work with UltraFast rules is to leverage the coding examples which are presented in Vivado Editor. These templates outline the different coding structures which can be used to comply with the UltraFast design rules.
As we progress through the stages of design implementation, we are able to open the synthesised and implemented design to report on the methodology.
This report should flag where we have forgotten to follow the UltraFast design methodology rules and enables us to go back and make any corrections necessary.
If you are not familiar with the UltraFast design methodologies, I recommend you sit down with a beverage of choice and spend the morning reading through them to better understand before you start your next design.
Doing so will probably save you a considerable amount of time when it comes to getting the best out of your design.