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MicroZed Chronicles: Updating Projects to Vitis

tech-blogs
Xilinx Employee
Xilinx Employee
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Editor’s Note: This content is republished from the MicroZed Chronicles, with permission from the author and Hackster.io.

 

One the key elements in our design is how we address upgrading from one version of design tools to the next.

If we have been developing our solution using a pre-2019.2 version of Vivado and using SDK to take advantage of the benefits and features of Vitis, we need to upgrade our design to Vivado 2019.2.

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The first step in doing this is to open the project in its current version of Vivado and archive the project. This way, if we hit issues, we always have a safe copy — regardless of if you are using a source control system such as Git.

You can find the archive command under File->Project->Archive.

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This will take a few seconds to run through, and once completed, you will see a notification the archive was successful.

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The next step is to open the Vivado design in 2019.2. When you point to the to be upgraded XPR file, you will notice the version is reported as Vivado 2019.1.1 in the file preview window.

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As the version of Vivado is different, you will next see a prompt asking if you desire to upgrade the project to the current version of Vivado.

Select automatic upgrade and click OK.

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As versions of the IP may have changes, Vivado will prompt you to report on the IP Status.

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Select Report IP Status. This will create a list of the IP in the design and identify which versions require upgrading.

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Click on the upgrade all button and the IP blocks, which require upgrading will be upgraded to the latest standard.

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Rerun the IP status report to make sure all of the IP is up to date, then finally generate a new but file and export the XSA.

Within the SDK, the project structure will be as shown below, with the Application, Board Support Package, and Hardware Definition listed under the project explorer.

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The structure is different within Vitis; however, we do not have to start from scratch.

From within Vivado, launch Vitis and select your desired working directory.

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Launching Vitis will prompt us to define the location of the workspace. For this project, I created a workspace within the Vivado project directory.

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Once Vitis is open, the next step is the import the existing SDK projects, which includes Hardware Definition, Board Support Package, and Application.

From the File menu select File->Import.

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The next dialog will allow us to select the elements of the eclipse workspace that we wish to import. Select the Application, BSP, and Hardware Definition.

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After a few minutes, you will see both the platform and application projects created under the Explorer window.

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Select the Platform project and right click on it and Update Hardware Specification.

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This will create a dialog to update the hardware definition. Point this to the XSA exported from the Vivado 2019.2 build.

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This will then show as the Platform is out of date once the new hardware specification has been updated.

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From the project menu, select Build and the project will be built, and the Platform definition will show as current.

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Now that we we have our design within the Vitis environment, we can begin to exploit the capabilities which are provided by Vitis!

 

See My FPGA / SoC Projects: Adam Taylor on Hackster.io

Get the Code: ATaylorCEngFIET (Adam Taylor)

Access the MicroZed Chronicles Archives with over 300 articles on the FPGA / Zynq / Zynq MpSoC updated weekly at MicroZed Chronicles.