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New Training Course: Advanced Timing Constraints for Vivado® Design Suite Users

Xilinx Employee
Xilinx Employee
1 0 781

Contributed by Rick Eggleton, FPGA Specialist & Trainer at Hardent and Reg Zatrepalek, FPGA Specialist & Trainer at Hardent

Achieving repeatable and reliable timing closure is every FPGA designer’s ultimate goal.

Hardent, a Xilinx Authorized Training Provider (ATP), is now offering a new 3-day advanced timing constraints training course designed to equip you with all the skills you need to achieve faster timing closure for your next design. 

Over 3 days of learning, your trainer will guide you through the Xilinx recommended process to improve design performance and reliability, and illustrate how to reduce design and implementation time by following these guidelines.

Training - Advanced Timing Closure Techniques for the Vivado Design Suite.png

Topics covered include:

  • UltraFast™ Design Methodology
  • Recommended HDL Coding Techniques
  • System vs. Local Design Resets
  • Baselining: Validating Your Design
  • Advanced Timing Analysis and Constraint Precision
  • Physical Optimization
  • Recognizing Congestion and How to Cope with It
  • Floorplanning for Design Success
  • And much more!

 

Training Dates & Locations

  • August 26–28, 2019 Live Online
  • September 10–12, 2019 in Montreal, QC
  • September 17–19, 2019 in Burlington, MA
  • October 1–3, 2019 in Coquitlam, BC
  • October 16–18, 2019 in Toronto, ON  
  • October 22–24, 2019 in Orlando, FL
  • November 5–7, 2019 in Huntsville, AL
  • December 9–11, 2019 in Ottawa, ON

 

Each class will be taught by one of Hardent’s FPGA Specialists.

Reg_Zatrepalek.jpgReg Zatrepalek

Rick_Eggleton.jpgRick Eggleton

 

 

 

 

 

 

 

 

 

 

 

 

 

Register now to save your spot!

Interested in taking a training course on another Xilinx topic? Check out Hardent’s complete list of Xilinx training courses.