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Output Delay

Xilinx Employee
Xilinx Employee
5 2 16.4K

 In this article, we will discuss the concept behind output_delay.

Output_delay with the –max option is relatively easy to understand. However, it is included here for the sake of completeness.

Output_delay with –min delay is a bit more tricky, and explaining it was the main motivation for writing this blog article.


Let us consider the following figure:

B represents the block/design portion to which we want to apply the constraints.

P is an output port of the block, on which output_delay needs to be applied.

F1 is the flop inside our block, which drives P.

F2 is the flop outside our block, which is supposed to sample the data coming out of P.

For convenience, let us assume that F1 and F2 are both driven by the same clock, and that there is no skew. The output_delay on P will also be specified with regard to the same clock.


For ease of understanding, we will use some specific numbers.

Consider the clock period to be 10 ns.


Max Delay

Assume that AFTER coming out of P, the signal will have a maximum delay of 7 ns before it is captured by F2.

This “7” should include: the time of flight from B to the next block, the time within the next block before it gets captured by F2, and the setup requirement of F2 itself.

This would be specified as: set_output_delay 7 –max ……

This, in turn means that the signal has up to 3 ns to reach “P”, after the clock edge.
Or, the signal can take a maximum time of 3 ns after the clock edge to reach “P”.

In terms of timing analysis, this is treated as if there is a hypothetical external flop, which has a setup requirement of 7 ns.
So, an output_delay specification of DMax means that the delay within the block has to be less than or equal to (Clock Period – Dmax).


Min Delay

Assume that AFTER coming out of P, the signal will take a minimum of 2ns before it is captured by flop F2.

Let’s also assume that the flop F2 has a HOLD requirement of 0.5 ns.

In this situation, the output delay specification should be: set_output_delay 1.5 –min

The figure of 1.5 is based on 2 – 0.5 (external delay – hold requirement on destination flop)
This in turn means that the signal can reach the port P as early as 1.5 ns BEFORE the clock edge.


“1.5 BEFORE the clock edge” is the earliest time that the signal is allowed to reach P. The signal is required to reach P later than this time.

So, the minimum delay that should be taken within the block = -(min output delay value specified). Note the negative sign to denote that it is BEFORE the clock edge.


This seems confusing, so let us try to justify these values.





Use of Min Specification in practice:


In general, there will be some time of flight. Especially as designs become larger, the signals will have to travel long distances from one block to another.


Because of this delay on the data path, the HOLD requirement will mostly be met on the destination flop. Thus, the min specification is not given that much importance.


For a lot of designs, we simply see: set_output_delay <value>, without any –min or –max specification.


For example: set_output_delay 7 …..


In this case, 7 is used for both the –max specification and for the –min specification.


Usually, the number chosen corresponds to the max external delay, as explained in the Max Delay specification.


For the min analysis, it is effectively a No-OP (i.e. no effect).


A large delay value will cause the internal minimal delay requirement to be a large negative number (-7 in this case).

The internal signal will have a finite +ve delay – which will definitely be larger than the large negative number.


We also sometimes see negative values for the –min option.

This means external delay will be negative, or, the value of the external delay is less than the HOLD requirement of the capturing device.

That means, F1 to P should have a +ve delay value, to ensure that the HOLD is met at F2.


Because the delay required from F1 to P is the negative of the min delay specification, we now have double-negatives.


This makes the min required delay (F1 to P) positive, which is more practical.


I am still very confused.


Could you please explain what "flight from P to F2" means? Does that mean the time for transmitting? How can it associated with hold-up time?



Xilinx Employee
Xilinx Employee

"time of flight from P to F2" means the time taken through the wire in reaching from "P" to "F2", i.e. the Interconnect delay.

The hold time, min specification is slightly confusing. So, it needs a bit patience (and, sometimes multiple reads).


Lets say, F2 has a HOLD requirement of 0.5ns.

That means, the signal has to arrive at F2 AFTER 0.5ns (or, later)


The "time of flight" will ensure some delay - and thus will help towards meeting this 0.5ns.


The higher is the time of flight, it is that much easier to meet the HOLD time at the destination, and that much more difficult to meet the SETUP time at the same destination.