Editor’s Note: This content is contributed by Andreas Braun (Design Engineer), Stefan Wiehler (Design Engineer) at Missing Link Electronics
Creating FPGA designs and maintaining Vivado® Design Suite projects can be a challenging task when working in a team with version control systems. The engineer must be able to track changes to a design, fully reproduce a project from HDL or TCL sources, and deliver a specific project state. For such tasks, Vivado tools are well suited with the ability to generate an archive file of a project or create a TCL file to reproduce a project state.
However, these mechanisms involve some manual work, and the flexibility can be a challenge to parameterize the design outside the Vivado Design Suite project. For this reason, we have created scripts that make these tasks easier. The idea is to provide the source HDL and TCL files of a project plus additional configuration files that create a Vivado Design Suite project from scratch. The build scripts are designed so that the user can develop independent parts of a project (flavors) in separate Vivado Design Suite projects and combine sources of different project parts in other configurations. Also, the build scripts are used to create target build artifacts such as IP XACTIPXACT packaging, simulation, synthesis, implementation, and bitstream generation.
In addition, MLE has released a set of convenience Makefiles for PetaLinux and Xilinx Software Development Kit (XSDK) with upcoming support for the Vitis™ unified software platform. These processing system Makefiles (or, in short, PSMake) are also available on GitHub.
To facilitate an FPGA Build Environment that can be automated, for example, for continuous integration (CI), and ensure fully reproducible results later in the development and product life cycle, the team at Missing Link Electronics has put together a collection of scripts. Currently focused on the Xilinx® Vivado tools (Version 2016.4 or newer) and tested under Ubuntu Linux 16.04 LTS and 18.04 LTS, this scripted FPGA Build Environment has been made available at GitHub under open source Apache 2.0 license.
We welcome any feedback and contribution from the FPGA ecosystem!