By Mike Thompson, Sr. Product Line Manager, Virtex UltraScale+ Portfolio at Xilinx
The world needs new classes of advanced chips and applications
One major trend we’ve seen in the market is the growing number of ASIC and SoC design starts in AI, 5G, autonomous driving, and hyperscale data centers. In those applications, whole systems are getting more complex as new chip architecture and integrated software are evolving. Another trend is that prototyping is rapidly growing as software developers and system designers want to test with real I/O traffic before their own silicon devices are available.
Xilinx Breaks Records!
Xilinx pioneered emulation-class devices almost a decade ago with the Virtex®-7 2000T FPGA and stacked silicon interconnect (SSI) technology. It allowed Xilinx to break through the limitations of Moore’s law and deliver the capabilities to satisfy the most demanding design requirements. With the groundbreaking UltraScale™ architecture, Virtex UltraScale VU440 FPGA became the successor, which gave 4X more capacity than competitive alternatives at that time. Last week, Xilinx introduced the world’s largest FPGA – the Virtex UltraScale+™ VU19P FPGA. Setting a new standard in FPGA design, the Virtex UltraScale+ VU19P FPGA features 9 million system logic cells. While Xilinx has achieved three consecutive generations of high-end leadership, Xilinx has broken its own record as a creator of the biggest FPGA. Twice.
The World’s Largest FPGA ever – Virtex UltraScale+ VU19P FPGA
With 9 million logic cells, up to 2,072 user I/O, and up to 80 28G transceivers, customers can emulate and prototype today’s most complex SoCs as well as the development of emerging, complex algorithms such as those used for artificial intelligence (AI), machine learning (ML), video processing, and sensor fusion. Customers can develop highly customized designs and validate emerging protocols. These next-generation AI-driven algorithms need to quickly move massive amounts of data in-and-out of the device to feed their algorithms. So, we’ve included 80 transceivers, the most ever in an emulation-class device. Emulation & prototyping customers have an endless demand for I/Os and memory bandwidth. Again, Xilinx listened. With over 2000 I/Os, this new FPGA delivers more external memory for debug, more interconnect for multi-FPGA environments, and enough interfaces for real I/O traffic.
Tools got better too
Having a big FPGA is one thing, using it to its maximum potential is another. One of the most critical factors in deploying these big devices is a robust development platform. The Vivado® Design Suite was invented to meet the needs of emulation-class designs. Xilinx has been optimizing compile times and quality of results for emulation-class designs for 3 generations. Vivado’s list of advanced features for emulation and prototyping includes: automated design closure assistance, interactive design suggestions, smart design tuning, compile-time efficiency, distributed parallel compilation, remote & multi-user debug support, and more. The latest Vivado release is our 3rd generation of emulation-class tools, IP, and design flows. And it comes with a well-documented design flow methodology and a mature ecosystem of other tools and IP that are tuned for this class of designs.
We’ve got the biggest FPGA on the planet. We’ve got the tools, design flows, and IP to support it. And we built this FPGA giant based on proven 3D IC assembly technology—so you can develop your next big thing.