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Webinar: Achieve Faster Timing Closure in the Vivado Design Suite with the UltraFast Design Methodology

Xilinx Employee
Xilinx Employee
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Xilinx Contact: Chris Dunlap, Xilinx Ecosystems Marketing Director

 

Do you often find yourself facing timing closure challenges? Get ready to improve your productivity by learning the top best practices and techniques needed to achieve faster timing closure!

 

Xilinx Authorized Training Provider Hardent will be presenting a free webinar on Tuesday, September 11 titled “Achieve Faster Timing Closure in the Vivado Design Suite with the UltraFast Design Methodology”.

 

hardent_training_webinar_Sep11_small.png

 

Over the course of one hour, you will get an overview of the FPGA design best practices and skills required to achieve faster timing closure using the UltraFast Design Methodology approach with the Vivado Design Suite.

 

You will discover:

 

  • The importance of baselining a design
  • How to identify the source of common timing issues using Vivado reports
  • How to apply timing closure techniques using the Vivado Design Suite
  • The importance of the UltraFast Design Methodology Checklist
  • How to automatically create a customized checklist for your own projects

 

The webinar will be followed by a brief demonstration to illustrate the techniques of baselining, as well as a live Q&A session with FPGA specialist & trainer Reg Zatrepalek. Don’t miss this chance to ask your questions to a Vivado expert!

 

Register now to save your spot!

Check out Hardent’s complete fall 2018 webinar schedule here.