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Why do I get reverse pessimism reduction during CPR?

Xilinx Employee
Xilinx Employee
0 0 5,793

Why do I get reverse pessimism reduction during CPR?

 

On Chip Variation leads to extreme pessimism in timing analysis.

A portion of this pessimism is recovered through what is called Clock Pessimism Reduction (CPR).

However, we often get queries from users saying that in their designs, instead of recovering a portion of the pessimism, the CPR section is actually doing the opposite, causing them to lose on timing (rather than gaining).

 

In a setup analysis, CPR is usually added to the destination clock path, thereby increasing the required time.

However, because the CPR in a user’s design has been reduced from the destination clock path, the required time moves earlier (rather than later).

As a result, the user thinks that they are losing time, rather than gaining.

In reality, the user is not suffering any loss.

 

When OCV analysis is performed, the source and destination paths are considered at different delay values.

However, for the “common” portion of the two paths, the delay should be the same.

CPR compensates for the delay differential, so that the delay values effectively become the same until the common point.

 

In order to better understand what is happening, consider the attached timing report.

(Thanks to Matsuyama-san of Xilinx Tokyo, for sharing this report from his sample design)

This report has been modified slightly to simplify it.

 

The source and the destination clocks share a common path until MMCME3_ADV_X1Y2.

After that, the source clock goes towards BUFGCE_X1Y48 while the destination clock goes towards BUFGCE_X1Y50.

 

Let us consider the delay until this common point (Vivado considers the output of the MMCM as the common point, even though the MMCM output pins of the two paths are different).

 

Looking at the source path in the timing report:

The Clock starts at time: 0  (line 21 of the timing report), and reaches the MMCM output at time: -3.218  (line 31 of the report).

So delay until this common point = -3.218

 

For the destination path:

The Clock starts at time: 3.33 (line 41 of the timing report), and reaches the MMCM output at time: 0.141 (line 50 of the report).

So the delay for the common point (on the destination path) is: 0.141 – 3.33 = -3.189

 

The destination path sees a larger delay (-3.189), than the source path (-3.218).

(Note the negative sign! Do not go just by the numeric value of the delays)

 

Thus, the destination path already has a higher delay, which needs to be compensated for.

And so, the clock pessimism, pulls IN the destination clock – and in doing so, reduces the required time.

 

Now, both the source and destination clocks have the same delay until the common point.

 The user has neither lost nor gained anything for the path until the common point (MMCM in this case).

 

This phenomenon of reverse pessimism reduction is typically seen in the presence of MMCM, and is more prevalent in 7 series devices than in UltraScale Devices.