The ability to work with OpenCL at higher levels of abstraction is increasingly important for FPGA developers. We can use OpenCL to develop applications for heterogeneous SoCs and acceleration cards, and to create HLS IP blocks.
I wanted to write a few blogs on OpenCL to highlight its increasing importance further. For this blog, I thought featuring an Alveo U50 acceleration card would allow me to focus on OpenCL in addition to the resulting acceleration.
Of course, first we must get the U50 up and running and installed in my Linux desktop. Once the board is physically connected, the first thing to do is boot the system and log into Linux.
As we enter the era of heterogeneous compute, where different processing engines in a single application take us to that next level of performance and efficiency, debug and trace tools have to evolve to keep up with devices.
Today, Xilinx adds a new product to its programming, debug, and trace module portfolio. The SmartLynq+ module is a high-speed debug and trace module primarily targeting designs using the Versal™ platform. It drastically improves configuration and trace speed. The SmartLynq+ module provides up to 28X faster Linux download time via the high-speed debug port (HSDP) than the SmartLynq data cable. For trace capture, the SmartLynq+ module is capable of speeds up to 10Gb/s via HSDP. That's 100X faster than standard JTAG! More rapid iterations and repetitive downloads increase development productivity and reduce the design cycle. This means that you no longer need to spend your precious time on debugging and instead can focus on the launch of your Versal based solutions.