To kick off this new year of blogs, I want to build upon the verification blogs previously started and examine how we can use VHDL frameworks such as UVVM. UVVM requires VHDL 2008 commands not currently supported by the Vivado Simulator so this leaves us with the choice of using either a commercial simulator such as ModelSim or an open source simulator such as GHDL.

As such, in this blog we are going to look at how to install GHDL and use it to simulate our VHDL designs. GHDL has been around for a several years, first released in 2002, and provides VHDL analysis, compilation, and simulation. What makes GHDL different to other simulations is that it compiles the VHDL into machine code by using one of several backends like GCC, LLVM, or its own internal mcode compiler. GHDL will run across Linux, Windows, and MAC platforms. I will be using a Windows instantiation for this example.

Xilinx is introducing two Versal™ ACAP evaluation kits: Versal AI Core series VCK190 evaluation kit and Versal Prime series VMK180 evaluation kit. Both the VCK190 and VMK180 evaluation kits come with the same set of accessories and have similar onboard interfaces. The main difference between the kits is...