Being able to leverage the power of programmable logic thanks to using High Level Synthesis allows us to significantly reduce development times. Of course, we want to leverage existing libraries in order to get the best from HLS developments and avoid having to reinvent the wheel each time.
Last year, I examined SLX FPGA and used it to optimise IP Cores for implementation in Vivado looking at security and industrial algorithms. Of course, things have moved on in the HLS world with the introduction of Vitis, last November. I was curious to see how SLX FPGA could be used in a Vitis bottom up flow. When working in a bottom up flow we use Vivado HLS to generate a Xilinx Object (XO) which is then added into Vitis for use later in the Vitis application. Such a bottom up flow allows us to focus on complex algorithms, verify thier performance and ensuring the optimization for programmable logic implementation provide the best implementation and are kept close to the algorithm.
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