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Adaptable Advantage Blog

Xilinx Employee
Xilinx Employee

The designs we implement in Vivado often use AXI interfaces. These might be AXI Lite for configuration and control, AXI Memory Mapped for high-speed memory mapped transfer, or AXI Stream for high-bandwidth streams.

These interfaces can be complex to verify, ensuring we get the protocol implemented correctly for bus transactions can present a challenge on its own. To help verify these interfaces in simulation, Vivado provides us with the AXI verification IP. This IP can be deployed in the following three different configurations:

  1. Generating AXI transactions as the bus master
  2. Responding to AXI transactions as a bus slave
  3. Pass-through in this mode is capable of AXI protocol checking

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