Adaptable Advantage Blog

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Adaptable Advantage Blog

Xilinx Employee
Xilinx Employee

Since starting this blog back in 2013, I get emailed questions from time to time. I definitely try to answer as many as I can and recently received an interesting one that I thought would make for a great example blog discussing what is actually occurring when we work with High-Level Synthesis.

The questioner was working with Vivado HLS 2020.1 and Vitis HLS 2020.1 and struggling to achieve the same operation in both tools. The code itself is simple and leverages the ap_wait_n() command to delay for several clock cycles.


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