If you have followed my blogs, courses, and/or webinars, you will know that I do a lot of high-reliability design. In fact, my first-ever article for Xilinx was on mission-critical design over 10 years ago in the Xcell Journal. This year, I have talked a lot about high-reliability design and ran a webinar on high-reliability design a few weeks ago. In addition, one of my recent Hackster projects was demonstrating how we can simulate single event upsets and the impacts on our FSMs, should they occur.
In all of these things, I mentioned how we can design state machines that do not lock up if subjected to a single event upset. With the proliferation of programmable logic into automotive applications and other high-reliability applications, I thought I would examine how we can implement safe state machines when using Vivado 2020.2 and Xilinx synthesis.
The Xilinx® Vivado® Design Suite’s IP integrator provides an excellent way to build custom designs using Xilinx IP or custom IP using block designs. Users can place these block designs into a hierarchical block, which can then be part of an overall hierarchical design. This is a great way to build complex hierarchical designs in a project.
But what if you’d like to use one of these great block designs that you’ve created in a different Vivado project? These block designs cannot simply be copied into another project and used in a block design within that project.
I recently learned of a simple method to use a block design from one project in a block design of a separate Vivado project.