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When we write code intended for HLS implementations, we tend to implement repetitive algorithms that process blocks of data — for example, signal or image processing.
As such, our HLS source code in either C or C++ tends to include several loops or nested loops. When it comes to optimizing, performance loops are one on the places we can start exploring optimization.
By default, HLS loops are kept rolled. This means that each iteration of the loop uses the same hardware. Of course, this provides the worst performance as each iteration is sequential.
5G is effectively reshaping wireless infrastructure and will provide a seamless solution for mobile and fixed communications, streaming video services, security monitoring, smart appliances, and even autonomous vehicles. This transformation, already underway, will change our daily lives. Today, Xilinx is at the forefront of 5G, offering a unique solution to engineers for exploration and validation of 5G systems. The Zynq® UltraScale+™ RFSoC has a proven track record as an ideal component in both 5G and other wireless systems, and Xilinx offers the ZCU111 Evaluation board to facilitate rapid prototyping and development.
Can you see something moving at 2.5 million miles an hour? For the Fermi Gamma-ray Space Telescope, it’s no problem. And when the FGST captured the pulsar PSR J0002+6216 (J0002 for short) shooting through Cassiopeia at the same speed, astronomers were able to trace its path back to the supernova where it was formed, about 6,500 light-years away.
Like the other incredibly powerful telescopes instrumental in capturing the clearest image of a black hole the world has ever seen, the FGST represents decades of space-age engineering. It also represents the frontier of open source real-time technology, supported by a Real-Time Executive for Multiprocessor System (RTEMS), the same technology that DornerWorks has recently ported to the Xilinx Zynq UltraScale+ MPSoC.