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Block RAMs (BRAM) are one of the key building blocks within our programmable logic designs. They are used for a range of applications from the ROM to FIFOs, and many stops in between.
Of course, one of the most popular applications of BRAMs is to act as data and instruction memories for our embedded processing solutions, e.g. MicroBlaze, or Arm Cortex-M1 and M3.
While it would be nice to get our software correct first time, unless it is very simple, it rarely happens. As such we need several design iterations, if each iterations needs to re-run the implementation to update the BRAM contents the time between tests is considerable. Although we can use JTAG debugging for some flows easily, e.g. MicroBlaze, there are use cases where we cannot, like when working with Arm cores without a DAP or separate JTAG.
Silicon Carbide (SiC) has gone from exotic to the mainstream with Tesla and other EVs’ adoption of the technology over the past five years. It’s no wonder because SiC solves several engineering challenges.
One of the main challenges in power electronics research is the rapid development of new topologies, e.g., modular multilevel converter (MMC). Even if new topologies promise better performance, with an increased number of states and possible switching combinations, they also require an increased computational complexity to drive them.