We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Adaptable Advantage Blog

Showing results for 
Search instead for 
Did you mean: 

Adaptable Advantage Blog

Xilinx Employee
Xilinx Employee


Today's designs are really complicated with many clocks domains, embedded processors, IPs, complex state machines and sometimes even HLS tool generated RTL from high level languages like C/C++. This complexity is exacerbated by many types of resets - processor, system, core, software and IP resets. Further complicating the reset architecture is the choice of synchronous and asynchronous resets, active high and active low resets which makes RTL coding style complicated too. Unfortunately, reset architecture is not thought about early in the design cycle leading to every designer deciding the fate of resets in their blocks which results in a reset strategy that is ad-hoc and poorly planned and implemented leading to many iterations, debug and sometimes even product recalls.


Read more
8 9 20.2K