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By Chetan Khona, Xilinx Industrial IoT Strategy


The Psychology behind Smart and Connected Products

If you are someone that wonders, with a healthy dose of cynicism, why seemingly everything is touting as being smart and connected these days, you might ask yourself, “Does that really need to be connected?” (I’m looking at you Bluetooth toothbrush with companion app—I manage to brush my teeth twice a day and scrub them all quite well without your help, thank you very much.) The actual answer is found in human psychology, not technology—or at least it was for me (cue flashback music): in the spring of 2011, Wired Magazine published an article on feedback loops, and not the kind you use in designing latches and flip-flops.


The article makes the argument for four stages in a feedback loop: 1) the capture, measurement, and storage of data; 2) data must be delivered, not in raw form, but in a persuasive way relevant to the context of the situation; 3) the information should be tied to practical options to address; 4) action should be taken that can then be fed back into the process again and again. This fairly well-understood paradigm, when applied to real-life situations as covered in the article, where nature and nurture often obscure the facts of the matter, was an eye-opener for me.


A Python Powered Framework for Smart and Connected Embedded Electronics

Fast-forward to today. The application of artificial intelligence, through analytics and machine learning techniques and in the context of the Internet of Things, follows this feedback concept quite rigorously. However, few frameworks encompass all elements of this process and even fewer make it relatively simple and easy. Xilinx has created one that delivers the goods—Python on Zynq, or PYNQ. You may have seen a pink-colored board at some point, but PYNQ is not limited to single target hardware, it is a framework that can work with any Zynq or Zynq UltraScale+ board, including your custom design.




The PYNQ framework offers you:

  • An unrivaled approach for capture and processing of multiple, heterogenous data streams, heavily leveraging the best parts of FPGA technology, parallelism, and determinism
  • The ability to visualize the on-chip data the same way some folks are only able to accomplish by shipping everything to the cloud or using expensive mathematical computing software
  • Support for a wide variety of libraries and packages under the control of the world’s most popular computer programming language, Python, such as ROS for robotics, Sci-Kit Learn for data mining and analysis, among many others
  • In a single device (the Zynq SoC portfolio), the entirety of the feedback loop: sensing, analyzing, deciding, and applying corrective action—all with best-in-class determinism and low latency
  • A built-in embedded web server that enables remote monitoring and updates, cloud co-processing, and is a key part of a software-friendly infrastructure

Learn More in as Little as 4 Minutes

All this capability is open-source, ready for prime-time, and available at no-charge. If you have 4 minutes, watch the SPYN motor control quick take video; if you have 15 minutes, read the PYNQ white paper; if you have 40 minutes, watch the recent webinar on PYNQ and SPYN on demand. If you have an hour, you can learn an incredible amount by doing all of the above, and you’ll be glad you did. Furthermore, you can leverage lots of community design examples ranging from machine vision to motor control to implementation of neural networks and much more. Go to: http://www.pynq.io/community.html

Xilinx has introduced the new Zynq UltraScale+ RFSoC ZCU111 Evaluation kit to enable RF-class analog design evaluation, bringing this disruptive technology to the masses to try for themselves. This kit is the first of its kind – featuring a Zynq UltraScale+ RFSoC, which integrates multi-gigabit ADC and DAC sampling capability with FPGA logic.


Mismatch in Timing Numbers between SDF and STA

by Xilinx Employee ‎01-18-2018 12:11 PM - edited ‎01-19-2018 09:32 AM

Sometimes, we get situations reported, where the timing numbers for individual elements during Vivado STA do not match the timing numbers shown in the Simulation SDF file, also generated by Vivado.

This article tries to explain various possible reasons why this discrepancy might appear, and how to interpret/reconcile them.


Best way to download Xilinx Design Tools

by Xilinx Employee ‎12-19-2017 01:36 PM - edited ‎12-19-2017 02:00 PM

Have you ever noticed while streaming Netflix videos, sometime the video blurs and then returns to high quality very quickly? Do you know what Netflix did in-between those few seconds? Along with adaptive bitrate streaming, it is basically continuously scanning for best CDN(Content Delivery Network) servers that can deliver data-packets faster.

Netflix may have mastered this but techniques to deliver large amount of data without any interruption have been around for few years now. For example, at Xilinx, we have been using Web Installer with such features that enables faster downloads without any interruptions.


Configurable Reporting

by Xilinx Employee ‎10-26-2017 11:07 AM - edited ‎10-26-2017 11:12 AM

Configurable Reporting - Xilinx Marketing - Xilinx PPG Enterprise Wiki

Converging a design can be tricky.  Usually when you push to solve one problem, changes ripple to other parts of your design and inevitably, other issues pop up.  In 2017.3 we are introducing a new feature that may help you solve this problem.  It’s called configurable reporting. 


Partial Reconfiguration involves loading configuration data into an active running design.  While there are some safeguards built into the silicon and bitstreams, such as the Device ID that ensures the correct part is targeted, there are techniques that must be understood and implemented as part of the user’s design.  Designers should follow these recommendations to ensure that partial reconfiguration is done safely and predictably.


Partial Reconfiguration Design Flow – The Configuration Analysis Report

by Xilinx Employee ‎10-13-2017 01:05 PM - edited ‎10-13-2017 02:00 PM

One unique aspect of the Partial Reconfiguration (PR) design flow is that there are multiple versions of the design that must be implemented through place and route.  These different “configurations” have common static design results but differing modules within each Reconfigurable Partition (RP).  Designers must set up timing constraints and floorplans that account for these different modules that will be swapped on the fly.  It can be challenging


In today's designs it is typical to have a large number of clocks that interact with each other. In order to ensure that Vivado optimizes paths that are critical, it is essential to understand how the clocks interact and how they are related – synchronous and asynchronous clocks.


AXI Interface Debug Using IP Integrator

by Xilinx Employee ‎09-14-2017 03:13 PM - edited ‎09-15-2017 11:21 AM

IP Integrator users connect IP blocks to create complex system designs. These block-based designs are typically constructed at the interface level and interfaces usually contain multiple busses and a large number of individual signals. Therefore, in order to easily debug these designs in hardware, it is necessary to verify the design interface-level connectivity.


Support for IP using "Standalone" .dcp Instead of .xci

by Xilinx Employee ‎09-14-2017 11:02 AM - edited ‎09-15-2017 10:56 AM

Beginning in 2017.1, we announced that xci and xcix files should be used for all Xilinx IP in our catalog.  This isn’t really new, we’ve actually been communicating that this is our primary recommendation for many years now.  And there are many important reasons for this.  The xci file is an xml file that captures all the configuration settings for the ip and more importantly points Vivado towards the plethora of files that are produced for ip; including - out of context synthesis, constraints, and simulation files.  The xci file is really how Vivado determines if the IP is “fully generated” or if there are any files missing.



In the project flow, Vivado keeps track of dependencies. As you invoke a particular step, the tool ensures that the previous step is complete


Terminology for IP Flow

by Xilinx Employee on ‎10-26-2016 04:54 PM

The Xilinx IP based flow uses terminology that is different from the terms used by typical RTL based designers.

As a result, we need to define certain terminology which might be unique to our IP Flow.

This blog article will attempt to demystify the terminology for flows related to IP.


Adding soft IP Cores such as MicroBlaze Subsystems or DDR Controllers as part of the Update Region of a Tandem with Field Updates Design.


Output Delay

by Xilinx Employee on ‎01-28-2016 01:55 PM

In this article, we will discuss the concept behind output_delay.


Vivado allows for a portion of the design to be synthesized Out-Of-Context (OOC).

The basic idea with an OOC flow is that a part of the design is synthesized by itself.


Constraining Asynchronous Clocks

by Xilinx Employee on ‎09-30-2015 02:40 PM

For asynchronous clocks, there are four ways to write the constraints.


Time Borrowing in Latches

by Xilinx Employee on ‎08-28-2015 09:28 AM

Static Timing Analysis applies a concept called Time Borrowing for latch based designs.

This blog post explains time-borrowing, and is relevant to cases where your design has latches, and your timing report has time-borrowing.


Ensuring Skew Control on Data Lines

by Xilinx Employee on ‎08-02-2015 10:44 PM

Sometimes, we might want a few signals to appear at more or less the same time time (i.e. the skew between these signals should not be beyond a certain limit).

A typical situation could be multiple bits of a bus, which should be arriving (almost) together.


Preventing Pulse Filtering in Simulation

by Xilinx Employee on ‎06-04-2015 10:44 AM

In general, if your design is passing simulation at a lower frequency but failing at a higher frequency, your first question should be whether the design is “timing clean” at the specified higher frequency.


Why do I get reverse pessimism reduction during CPR?

by Xilinx Employee ‎04-15-2015 11:08 PM - edited ‎04-15-2015 11:20 PM

On Chip Variation leads to extreme pessimism in timing analysis.

A portion of this pessimism is recovered through what is called Clock Pessimism Reduction (CPR).

However, we often get queries from users saying that in their designs, instead of recovering a portion of the pessimism, the CPR section is actually doing the opposite, causing them to lose on timing (rather than gaining).


About the blogger...

by Xilinx Employee ‎03-20-2015 03:53 PM - edited ‎05-21-2017 07:39 AM

This blog will focus on technical articles explaining how to achieve something specific with XLNX tools and solutions, or explaining some specific aspect of the tool behavior.