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Adventurer
Adventurer
486 Views
Registered: ‎12-04-2019

Alveo DMB-1 or PCie link down after flash programming

Hello

My custom design has PCIe and I have followed the 'Custom Flow' procedure from the documentation. The only mistake I did was I dint disable the PCIe before the flash programming. The PCI link has gone down and the LED lights up only for a couple of seconds during the cold reboot.  I have even tried the ideas given in this thread ( https://forums.xilinx.com/t5/Alveo-Accelerator-Cards/Alveo-U50-DMB-1-No-device-detected-on-target/td-p/1108140 ) but it was of no use. Vivado's hardware manager too doesn't detect the card.

Any ideas as to how to reset the card without the PCIe. 

P.S. xbutil and xbmgmt throw an error saying the card has not been found.

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Xilinx Employee
Xilinx Employee
462 Views
Registered: ‎10-19-2015

@naarayananrao 

xbutil and xbmgmt will not be available to you if you create a custom project design instead of a design in Vitis. 

Likely you have created a design that does not drive the HBM cat trip pin to the satellite controller correctly. 

Here is an excerpt from another thread on how you may try to recover the card

"I seem to be able to recover the U50 by attaching the JTAG programmer from a secondary computer and having Vivado Hardware Manager open and ready to talk to the FPGA when it first powers up. In that state, the U50 does not power off like it does when the JTAG programmer is not actively connected to it. Even if the programmer is physically connected, you cannot recover from the computer it is plugged into since the Hardware Manager in the Vivado GUI has to be up and connected to the JTAG programmer in order to catch the U50 before it powers itself off."
 
Please try this and let us know if this works. 
Regards,
M
 
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Adventurer
Adventurer
458 Views
Registered: ‎12-04-2019

I have a quick silly question.

The XDC file says that we have to drive the cat_trip pin to avoid power rail failures.

I am using the following commands :

set_property PACKAGE_PIN J18 [get_ports "HBM_CATTRIP"]
set_property IOSTANDARD LVCMOS18 [get_ports "HBM_CATTRIP"]

 

But when I open the synthesized design there are critical warnings that the set_property and get_ports don't return any value.

Should the QSFP28 IP be included for this to work? In my current design, I have the XDMA IP and doesn't it have the HBM settings. Not sure what I am supposed to do here

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Xilinx Employee
Xilinx Employee
381 Views
Registered: ‎10-19-2015

Hi @naarayananrao 

You need to have a top level port in your design called "HBM_CATTRIP" in order for those XDC constraints to work. 

The cattrip signal should be coming from the HBM, if there is no HBM in the design, create a wire and drive it to 1'b0 and call that HBM_CATTRIP.

Regards,

M

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Adventurer
Adventurer
366 Views
Registered: ‎12-04-2019

Hello @mcertosi 

Is it possible to add the wire in Vivado or do I need to edit the schematic using the ISE editor?

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Xilinx Employee
Xilinx Employee
364 Views
Registered: ‎10-19-2015

Hi @naarayananrao 

You should make changes in an RTL / Text editor. I suppose you could edit a schematic in ISE if you are familiar with that flow, but I can't help you with that. Ultimately you need this defined in the top level of your RTL designed so you can assign the wire to a port. 

Regards,

M

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