08-31-2019 06:10 AM
I need interfacing xilinx SDAccel generated block diagram imported in Vivado block design part with an existing QSFP port in U200 Alveo card. Is there any related example or document or application note about this? Is this possible at all?
Thanks for your attention and quick responses...
09-05-2019 08:44 AM
Here is the flow for using Alveo with the QSFP ports
10-11-2019 01:21 PM
Slightly different board but the same family - Alveo U280:
I've been using the flow described in the https://www.xilinx.com/support/answers/71981.html.
I have connected the 100G Ethernet Subsystem and the QSFP Sideband signals through the AXI GPIO for the (lowspeed signals), howver I don't get an output clock coming from the CMAC IP.
Any idea what I'm doing wrong?
05-18-2020 10:27 AM
The u280 has different connections than the u200. The satellite controller might be controlling the low speed signals of the QSFPs.
This should be handled in a new thread so other users can find this information easily as it is a common question.
Can you make a new thread and include if you are using an ES1 or production u280?