cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
lichengguo777
Visitor
Visitor
472 Views
Registered: ‎07-12-2019

Alveo U250 XDC mismatch with DDR4 controller

I'm trying to implement the DDR4 controller on U250. The DDR4 controller is configured according to the U250 user guide.

However, the interface of the MIG IP is somewhat different from what's in the given XDC file for the board. For example, the IP has port "act_n", while the XDC has "ACT_B". Many ports have bit-width mismatch.

All the differences are listed below in the format "IP port -> XDC port":

act_n -> ACT_B

adr[16:0] -> ADR[17:0]

ck_c -> CK_C[1:0]

ck_t -> CK_T[1:0]

cke -> CK_E[1:0]

cs_n -> CS_B[3:0]

odt -> ODT[1:0]

 

ddr_interface.png

Given these mismatches, how am I suppose to implement the DDR controller?

Thanks for your help.

Tags (5)
0 Kudos
Reply
1 Reply
mcertosi
Xilinx Employee
Xilinx Employee
418 Views
Registered: ‎10-19-2015

Hi @lichengguo777 

Good catches. The XDC files posted online continue to be a point of problems. We are working on correcting them. 

For now the best flow for you is to use the board aware flow described in these answer records below:

https://www.xilinx.com/support/answers/71981.html

https://www.xilinx.com/support/answers/71754.html

When you drop the DDR4 IP into an IPI block, the board files should take care of all the pinouts and IP configurations that are already on the card. 

Also, you might want to search the forums to see if others have encountered this problem.

Regards,

M

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Reply