I'm trying to implement the DDR4 controller on U250. The DDR4 controller is configured according to the U250 user guide.
However, the interface of the MIG IP is somewhat different from what's in the given XDC file for the board. For example, the IP has port "act_n", while the XDC has "ACT_B". Many ports have bit-width mismatch.
All the differences are listed below in the format "IP port -> XDC port":
act_n -> ACT_B
adr[16:0] -> ADR[17:0]
ck_c -> CK_C[1:0]
ck_t -> CK_T[1:0]
cke -> CK_E[1:0]
cs_n -> CS_B[3:0]
odt -> ODT[1:0]
Given these mismatches, how am I suppose to implement the DDR controller?