01-02-2020 06:54 AM
The XDC file that can be downloaded from the Xilinx site is not correct, the IO Standards are not defined correctly (defaulted to LVCMOSxx) for the interfaces. Note that there are mistakes in the U250 & U200 files as well (they can't compile as is).
I've edited that U280 file based on the U250 and U200 xdc files, I've corrected errors through the synthesis/implementation/bit-stream phases in that xdc, I've added the bistream header, etc, etc.
I'll attach what I have, please review it and see if I did anything wrong, or if there are still basic xdc corrections from Xilinx needed.
Also, I've tried to build a custom designs, one with the Xilinx QDMA IP, one with a bare PCIe Endpoint, both do not show up in the server's lspci list (they used to with the factory image). There are two pcie reference clocks (PCIE_CLK0_N/P, PCIE_CLK1_N/P), I first tried with clk0 but that produced errors, I changed to clk1 and was able to generate a bit-stream and from that an mcs file. I successfully program the device, I can see some basic debug/debug-core, but the PCIe endpoint does not appear, and the phy/link is not up - I'm concered there is still a basic PCIe clock selection issue, or perstn reset issue. I'll bring this up in a separate post.
Any feedback/input would be greatly appreciated.
01-02-2020 07:46 AM
Dumb question - how do I attach the xdc file? Says file doesn't match format.
And, it is too large to paste here.
01-02-2020 08:24 AM
The XDC file errors are expected to be fixed in an upcoming release.
For now, could you try using the board files from our XilinxBoardStore github page? https://github.com/Xilinx/XilinxBoardStore/tree/master/boards/Xilinx
I've seen XDC files attached here without error in the past. Could you maybe try zipping it and posting a zip file?
01-02-2020 10:26 AM
I see a difference in my xdc for perstn versus the latest part0_pins.xml you pointed me to under the boards - github link.
I'll go through that and see if there is anything else wrong in my file.
01-02-2020 10:56 AM
From the latest board github repo, file part0_pins.xml, I see I had a number of IOSTANDARD values incorrectly specified. There were also some pin names on the xdc that did not match that part0 file so I changed them. Including the one associated with pin D31 that another AR says to drive to 0.
Here is a newer version of my xdc.
01-04-2020 07:26 PM
Moving on in my debug phase I found that some of the XDC file's DDR4 signals appear to be on the wrong pins/balls. I was getting several errors: "[Vivado 12-1411] Cannot set LOC property of ports"... I went into the implementation's ball diagram and found balls in the error area that said that the DQ... was fixed to a ball but the XDC had a different signal on that ball. So the errors narrowed down the four-bit grouping and the pin diagram helped me fix it. Now I compile with no errors. Not to say what I have is correct, yet, but it is better than what was there before (at least I don't get the errors).
Here is my latest XDC, any feedback/corrections would be greatly appreciated.
01-05-2020 07:12 PM
By the way, you mention using the board files, which I have updated as you an others suggested, but without an XDC you can't run a "custom" compile without errors. I tried.
01-06-2020 12:38 PM - edited 01-06-2020 12:39 PM
Can you describe the flow you are using the board files with?
You'd need to be designing in the block diagram flow for the board files to work. Please use AR#71981 specifically, take a look at step 2.
If the board files can't get you working with the flow above, please let me know as that would require another bug fix.
We are still working on xdc files.
Here is an XDC generated from a DDR4 example built against the u200 and 1 DDR4 kernel. This should have DDR4 and PCIe constraints. Does this help?
02-24-2020 09:56 AM
Update to the thread: New U280 XDC file has been uploaded to the Alveo product page, please review the changes, as they will likely significantly improve the user experience and design availability.