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Observer
Observer
961 Views
Registered: ‎11-02-2018

Alveo U50 PCIe project

Hi,

I am currently trying to create a project similar to this one: https://www.youtube.com/watch?v=TzzzM97L4HI on an Alveo U50 using Vivado 2019.2.1

My goal is to create some kind of PCIe communication between my host PC and my board as a first step of a project that consists in communicating two U50 boards and apply a PTP filter between them.

 

I am having lots of issues following the video tutorial:

1) I can't add the DDR4 block as it fails to create the IP core:

Screenshot from 2020-03-02 09-45-14.png

2) If I try to synthesize just the xdma_0 block, I have a Multiple block runs Failed error.

Screenshot from 2020-03-02 09-45-14 (1).png

This is my log:

 

start_gui
create_project project_1 /Vivado2019.2/Vivado/2019.2/bin/project_1 -part xcu50-fsvh2104-2-e
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/Vivado2019.2/Vivado/2019.2/data/ip'.
create_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 6858.973 ; gain = 169.633 ; free physical = 10978 ; free virtual = 15000
set_property board_part xilinx.com:au50:part0:1.0 [current_project]
set_property target_language VHDL [current_project]
create_bd_design "design_1"
Wrote  : </Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd> 
update_compile_order -fileset sources_1
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0
INFO: [Device 21-403] Loading part xcu50-fsvh2104-2-e
xit::create_sub_core: Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 8197.098 ; gain = 1147.195 ; free physical = 9795 ; free virtual = 13813
create_bd_cell: Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 8197.102 ; gain = 1174.883 ; free physical = 9712 ; free virtual = 13730
apply_board_connection -board_interface "pci_express_x8" -ip_intf "xdma_0/pcie_mgt" -diagram "design_1" 
INFO: [board_interface 100-100] current_bd_design design_1
INFO: [board_interface 100-100] set_property CONFIG.PCIE_BOARD_INTERFACE pci_express_x8 [get_bd_cells -quiet /xdma_0]
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
INFO: [board_interface 100-100] create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x8
INFO: [board_interface 100-100] connect_bd_intf_net /pci_express_x8 /xdma_0/pcie_mgt
apply_board_connection: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 8218.215 ; gain = 21.113 ; free physical = 9749 ; free virtual = 13767
apply_board_connection -board_interface "pcie_perstn" -ip_intf "xdma_0/RST.sys_rst_n" -diagram "design_1" 
INFO: [board_interface 100-100] current_bd_design design_1
INFO: [board_interface 100-100] set_property CONFIG.SYS_RST_N_BOARD_INTERFACE pcie_perstn [get_bd_cells -quiet /xdma_0]
INFO: [board_interface 100-100] create_bd_port -dir I pcie_perstn -type rst
INFO: [board_interface 100-100] set_property CONFIG.POLARITY  /pcie_perstn
INFO: [board_interface 100-100] connect_bd_net /pcie_perstn /xdma_0/sys_rst_n
INFO: [board_interface 100-100] set_property CONFIG.POLARITY ACTIVE_LOW /pcie_perstn
apply_board_connection: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 8220.215 ; gain = 2.000 ; free physical = 9724 ; free virtual = 13742
endgroup
apply_bd_automation -rule xilinx.com:bd_rule:xdma -config { accel {1} auto_level {IP Level} axi_clk {Maximum Data Width} axi_intf {AXI Memory Mapped} bar_size {Disable} bypass_size {Disable} c2h {1} cache_size {32k} h2c {1} lane_width {X8} link_speed {8.0 GT/s (PCIe Gen 3)}}  [get_bd_cells xdma_0]
INFO: [board_rule 100-100] set_property CONFIG.USE_BOARD_FLOW true [get_bd_cells /util_ds_buf]
INFO: [board_rule 100-100] set_property CONFIG.DIFF_CLK_IN_BOARD_INTERFACE pcie_refclk [get_bd_cells /util_ds_buf]
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
INFO: [board_rule 100-100] create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk
INFO: [board_rule 100-100] set_property CONFIG.FREQ_HZ 100000000 /pcie_refclk
INFO: [board_rule 100-100] connect_bd_intf_net /pcie_refclk /util_ds_buf/CLK_IN_D
INFO: [board_rule 100-100] set_property CONFIG.FREQ_HZ 100000000 /pcie_refclk
validate_bd_design
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
ERROR: [Ip 78-140] conversion to double from string is failed
INFO: [Common 17-14] Message 'Ip 78-140' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
integer value too large to represent
ERROR: [IP_Flow 19-3477] Update of parameter 'PARAM_VALUE.C0.DDR4_AXIADDRESSWIDTH' failed for IP 'design_1_ddr4_0_0'. integer value too large to represent
ERROR: [IP_Flow 19-3428] Failed to create Customization object design_1_ddr4_0_0
CRITICAL WARNING: [IP_Flow 19-5622] Failed to create IP instance 'design_1_ddr4_0_0'. Failed to customize IP instance 'design_1_ddr4_0_0'. Failed to load customization data
ERROR: [BD 41-1712] Create IP failed with errors
ERROR: [BD 5-7] Error: running create_bd_cell  -vlnv xilinx.com:ip:ddr4:2.2 -type ip -name ddr4_0 .
create_bd_cell: Time (s): cpu = 00:00:19 ; elapsed = 00:00:34 . Memory (MB): peak = 8609.090 ; gain = 251.883 ; free physical = 9423 ; free virtual = 13465
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.
endgroup
make_wrapper -files [get_files /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd] -top
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
Wrote  : </Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd> 
Wrote  : </Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui> 
VHDL Output written to : /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/synth/design_1.vhd
VHDL Output written to : /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/sim/design_1.vhd
VHDL Output written to : /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
add_files -norecurse /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
launch_runs synth_1 -jobs 4
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
Wrote  : </Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd> 
Wrote  : </Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui> 
VHDL Output written to : /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/synth/design_1.vhd
VHDL Output written to : /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/sim/design_1.vhd
VHDL Output written to : /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
INFO: [BD 41-1029] Generation completed for the IP Integrator block xdma_0 .
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/adrianwhale/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf .
Exporting to file /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
Generated Block Design Tcl file /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
Generated Hardware Definition File /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.srcs/sources_1/bd/design_1/synth/design_1.hwdef
INFO: [IP_Flow 19-5642] Done with IP cache export for multiple IPs
[Mon Mar  2 09:42:01 2020] Launched design_1_xdma_0_0_synth_1, design_1_util_ds_buf_0_synth_1...
Run output will be captured here:
design_1_xdma_0_0_synth_1: /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.runs/design_1_xdma_0_0_synth_1/runme.log
design_1_util_ds_buf_0_synth_1: /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.runs/design_1_util_ds_buf_0_synth_1/runme.log
[Mon Mar  2 09:42:01 2020] Launched synth_1...
Run output will be captured here: /Vivado2019.2/Vivado/2019.2/bin/project_1/project_1.runs/synth_1/runme.log
launch_runs: Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 8738.238 ; gain = 77.160 ; free physical = 9165 ; free virtual = 13318

 

Thank you in advance 

This video walks through the process of creating a PCI Express solution that uses the new 2016.1 DMA for PCI Express IP Subsystem. The first part of the vide...
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Observer
Observer
947 Views
Registered: ‎09-26-2018

Hi,

to fix

ERROR: [Ip 78-140] conversion to double from string is failed

just change Settings->Language Format to American English from whatever you allready have. Then logout/reboot and try again

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Xilinx Employee
Xilinx Employee
905 Views
Registered: ‎12-10-2013

@adrianwhale 

Please note that the video you are watching is not specific to the U50, and there will be many architectural differences.  You will need to review the User's Guide for the U50 on how to create a bitstream / mcs, among others.

For your first issue - there is no DDR on a U50 card.  The memory is all HBM.

I would suggest you also look into the Platform Acceleration flow, as it already has all the infrastructure built in for host to card and card to host transfers (via XDMA), drivers, DFX (PR), connectivity to HBM, and Peer-to-Peer.   You can create RTL or OpenCL kernels to do the user operations on the data, but the heavily lifting is done. 

If you are not a very experienced Vivado user, the "Custom" flow is not recommended. 

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Observer
Observer
853 Views
Registered: ‎11-02-2018

Thank you so much for your response.

I am aware that the U50 doesn't have a ddr and that the video I am watching doesn't completely apply to my main project. I just wanted to prove that I have PCIe communication between my PC and my board, as a step 1.

 

Indeed I am not a very experienced Vivado user. I am using 'custom flow' because I will need to integrate an IP core that my team has already created for an older board into de Alveo. I have tried to follow the Vitis tutorials but I am not sure where could an existing IP core be integrated using that flow.

 

I wold very much appreciate some kind of guidance for my end project: communicating two Alveo U50 using a QSFP, adding timestamp to the packets and applying a PTP filter. I have no preference regarding what flow to follow, just whatever is easier and faster.

 

 

 

 

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Observer
Observer
837 Views
Registered: ‎09-26-2018

As I aware, you do need HW-DMB-1-G (JTAG Programmer) for accessing U50 FPGA. The ALVEO (XRT) shell does not have QSFP28 support, yet.

I don't get it, why ALVEO U50 doesn't have JTAG on board, while U200/250/280 have?

 

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Xilinx Employee
Xilinx Employee
814 Views
Registered: ‎12-10-2013

@kschmidt 

The USB-JTAG connector was removed per customer security requirements such that the programming interface was inaccessible when installed in a Data Center environment.  As the primary use case is Data Center and Vitis flow, the expectation is that programming is done over PCIe in-band.

@adrianwhale 

Have you looked at the Vitis flow with an RTL kernel?   That would be where custom IP could be inserted into the card with the Acceleration Platform providing the infrastructure.   We don't have any "custom flow" specific tutorials or examples.  If you are looking to do prototyping or pure development - I would highly recommend the Vitis flow or a Xilinx development kit that has many more resources available.   The resources available for "custom flow" are few, and you lose a lot of critical features provided by the Acceleration Platform, particularly on the U50.   Please carefully review the information in UG1371 and the XDC, and this is the totality of available information. 

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Observer
Observer
776 Views
Registered: ‎11-02-2018

Thank you so much for your answers.

If I understand correctly, I should follow this tutorial: https://github.com/Xilinx/Vitis-Tutorials/blob/master/docs/getting-started-rtl-kernels/README.md and instead of adding the Vadd_A_B files, I should use my own. Am I right?

Can I create my own block design in the Vivado part of the process and then generate the RTL Kernel and continue using Vitis as described in the tutorial? Do I need to include a PCIe block in Vivado, or it is already included in the kernel that is going to be generated?

 

Again, thank you for all the answers. This is completely out of my zone of expertise.

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Observer
Observer
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Registered: ‎11-02-2018

There is another thing that neither my tutor not I are sure how to achieve: we would like the host PC to detect the U50 board as a NIC card.
I have read that the new Alveo U25 would be ideal for this task, as it is sold as a SmartNIC acceleration card, but I have found no documentation on how to use it or wether it is possible or not to do the same thing with the U50.
Thank you in advance
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Xilinx Employee
Xilinx Employee
718 Views
Registered: ‎12-10-2013

Hi @adrianwhale 

To do an Ethernet application, you would need an Acceleration Platform which had a streaming architecture - like the U280 QDMA.  You are correct that the U25 is probably going to be closer to your needs.  As the U25 has just announced, the rest of the information beyond the product brief is still coming.

 

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Observer
Observer
685 Views
Registered: ‎11-02-2018

Thank you so much for your answer. You have saved me weeks of work.

Just to make sure, the U50 will not be able to show up as a NIC in my host PC, right? Will there be any U25 project that could be adapted to de U50 to do so?

Again, thank you for your answers.

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Observer
Observer
655 Views
Registered: ‎11-02-2018

could you give an estimation on when the U25 documentation will be available?

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Xilinx Employee
Xilinx Employee
640 Views
Registered: ‎12-10-2013

Hi @adrianwhale 

Please get in contact with your Xilinx sales representative for roadmap information.

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Observer
Observer
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Registered: ‎07-26-2018

Hi All, we are looking for TCL scripts for programming U50 with the DMB programmer.  Do you have sample TCL scripts for programming with DMB?  Thanks!

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Xilinx Employee
Xilinx Employee
374 Views
Registered: ‎10-19-2015

Hi @jszefer 

I don't have any pre-packaged TCL scripts to provide. 

However, Vivado prints out every TCL command it runs in blue in the Vivado TCL console. The flow we usually recommend is to do the process once using Vivado, then copy out all the commands you ran and add them to your own tcl script. 

When you have the DMB and a USB cable connected the programming method is identical to just having a JTAG or USB to JTAG connection. 

Hope that helps.

Regards,

M

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