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Observer
Observer
937 Views
Registered: ‎05-31-2018

Alveo U50 pinout and clocks

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Hi,

I'm starting an Alveo U50 design in Vivado flow. The master XDC file is provided on Xilinx website, but the details about the pinout (i.e, oscillator clock frequency and pinlocs) is still hard to understand with the XDC file. Is there any detailed description for Vivado-based design with U50 card?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

@irage_sd and @yosana 

XTP576 is very clear, grab it from this link https://www.xilinx.com/products/boards-and-kits/alveo/u50.html#documentation

This should answer your questions.

Regards,

M

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Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

The released information available is here:

https://www.xilinx.com/support/documentation/boards_and_kits/accelerator-cards/ug1371-u50-reconfig-accel.pdf

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Observer
Observer
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Registered: ‎05-31-2018

UG1371 (and Master XDC) doesn't tell about clock frequency of the on-board oscillators (and even location of HBM reference clock :( )
OK, I should read board files (board.xml and part0_pins.xml) for further details...

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Observer
Observer
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Registered: ‎10-23-2019

Did you found 300 Mhz differential(LVDS) clock pins?

is it cmc_clk_p and  cmc_clk_n?

Thanks and  Regards

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Xilinx Employee
Xilinx Employee
648 Views
Registered: ‎10-19-2015

@irage_sd and @yosana 

XTP576 is very clear, grab it from this link https://www.xilinx.com/products/boards-and-kits/alveo/u50.html#documentation

This should answer your questions.

Regards,

M

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Observer
Observer
564 Views
Registered: ‎10-23-2019
@mcertosi
Thanks,
I have gone through it.
My Conclusion: In u50DD Engineering Sample Board. 300MHz board clock is not available. There are 100MHz, 322MHz and 161MHz clocks available. I am correct with my conclusion right ?
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Xilinx Employee
Xilinx Employee
543 Views
Registered: ‎10-19-2015

Hi @irage_sd 

There is no 300 MHz clock on the board. What do you need it for?

Regards,

M

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Observer
Observer
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Registered: ‎10-23-2019

@mcertosi 

Thanks, I am porting one of my designs to u50DD board. The design required a 300MHz clock. But anyways have made appropriate changes to the design in order to port it to u50DD board. I am generating the 300MHz clock using MMCM block.  

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