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Observer
Observer
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Registered: ‎03-26-2018

Alveo u200 clock source and debug pins

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Hi,

We are working with IPI (vivado 2019.2) on a custom build. We are building our project to work on the Alveo u200. We want to use an aurora link QSFP0 (line rate 5.0 Gb/s, 1 lane (Quad X1Y5), ,Gt refClk 156.25 MHz, init clk 50 MHz, Tx only simplex and framing).

Do we have to program the clock found on QSFP0_CLOCK (Pins P10/P11) ? Which value is by default? How do we do that?

There are also three other "clock sources" which might be of interest:

  1. USER_SI570_CLOCK (pins AV1/AU9)
  2. MTG_SI570_CLOCK0_C (pins M10/M11)
  3. MTG_SI570_CLOCK1_C (pins T10/T11)

What are the default values? Is it possible to program them?how?

 

It is possible to use a Axi_gpio module connected to the QSFP0 lowSpeed IOs?Which pin does it really drive? 

 

I also saw that there are small pin headers on the board side? can it be used for probing ?

 

Thanks in advance for your help!

Cheers

JP

 

 

 

 

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Xilinx Employee
Xilinx Employee
401 Views
Registered: ‎10-19-2015

Re: Alveo u200 clock source and debug pins

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Hi @jpbb 

I believe the default clock speed is 156.25 MHz for the USER_SI570_CLK. At this time users are not able to interact with the clock to change the frequency.

In most designs the DDR4 IP is the bottlneck and so we encourage designers to use the AXI clock generated from the DDR4 IP as the kernel clock. @2400MTs, the DDR4 user clock is 300MHz 

The below pin definitions are in the XDC file, is this not what you are looking for? 

AY20 - QSFP1 MODSELL = qsfp1_lowspeed_2
BC18 - QSFP1 RESETL = qsfp1_lowspeed_1
BC19 - QSFP1 MODPRSL = qsfp1_lowspeed_3
AV21 - QSFP1 INIT LS = qsfp1_lowspeed_4
AV22 - QSFP1 LPMODE = qsfp1_lowspeed_0
BE16 - QSFP0_MODSELL_LS = qsfp0_lowspeed_2
BE17 - QSFP0_RESETL_LS = qsfp0_lowspeed_1
BE20 - QSFP0_MODPRSL_LS = qsfp0_lowspeed_3
BE21 - QSFP0_INTL_LS = qsfp0_lowspeed_4
BD18 - QSFP0_LPMODE_LS = qsfp0_lowspeed_0

 In our application we would need to export two IOs to SMA contacts (for generating  external pulses). That's why I would like to know if there are such IO, and if so which IO voltage domain?

At this time there is no way to use any pins for generating external pulses. 

Let me know if there's any additional clarification I can provide. 

Regards,

M

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Xilinx Employee
Xilinx Employee
435 Views
Registered: ‎10-19-2015

Re: Alveo u200 clock source and debug pins

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Hi @jpbb 

Do we have to program the clock found on QSFP0_CLOCK (Pins P10/P11) ? Which value is by default? How do we do that?

No. The QSFP clock pins are 156.25MHz by default. It looks like you can configure the qsfp0/1 clock for other common Ethernet clock frequencies by following the flow in AR#71981 and using the board files found here, in our github board repo.

What are the default values? Is it possible to program them?how?

There is no user access to the MTG_SI570_CLOCK0_C and MTG_SI570_CLOCK1_C at this time. What in your design requires interacting with the MGT interface of the QSFP such that you'd need to know the clock speed? 

What document shows you USER_SI570_CLOCK (pins AV1/AU9)?

It is possible to use a Axi_gpio module connected to the QSFP0 lowSpeed IOs?Which pin does it really drive? 

If you'd like to, I do not see why you could not use axi_gpio module connected to the low speed IOs. Can you elaborate on your second question?

I also saw that there are small pin headers on the board side? can it be used for probing ?

Xilinx doesn't recommend it. The small pin headers were for internal use only.

Regards,

M

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Observer
Observer
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Registered: ‎03-26-2018

Re: Alveo u200 clock source and debug pins

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Hi M,

I was planning to use USER_SI570 clock as system clcok. I do not want ot touch the SYSCLK connected to the DDR4 , I might use them later on.

I made a typo error . In the alveo-u200-xdc.xdc, USER_SI570_CLK is connected to AV19/AU19.

 

I do not understand which are the low speed IOs connected to QSFP0/1. That was my question. Is it _MODSKLL? _INT_LS? LPMODE? RESETL?

 

probing / pin-header:

 In our application we would need to export two IOs to SMA contacts (for generating  external pulses). That's why I would like to know if there are such IO, and if so which IO voltage domain?

 

Thanks for your quick answers

cheers

JP

 

 

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Xilinx Employee
Xilinx Employee
402 Views
Registered: ‎10-19-2015

Re: Alveo u200 clock source and debug pins

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Hi @jpbb 

I believe the default clock speed is 156.25 MHz for the USER_SI570_CLK. At this time users are not able to interact with the clock to change the frequency.

In most designs the DDR4 IP is the bottlneck and so we encourage designers to use the AXI clock generated from the DDR4 IP as the kernel clock. @2400MTs, the DDR4 user clock is 300MHz 

The below pin definitions are in the XDC file, is this not what you are looking for? 

AY20 - QSFP1 MODSELL = qsfp1_lowspeed_2
BC18 - QSFP1 RESETL = qsfp1_lowspeed_1
BC19 - QSFP1 MODPRSL = qsfp1_lowspeed_3
AV21 - QSFP1 INIT LS = qsfp1_lowspeed_4
AV22 - QSFP1 LPMODE = qsfp1_lowspeed_0
BE16 - QSFP0_MODSELL_LS = qsfp0_lowspeed_2
BE17 - QSFP0_RESETL_LS = qsfp0_lowspeed_1
BE20 - QSFP0_MODPRSL_LS = qsfp0_lowspeed_3
BE21 - QSFP0_INTL_LS = qsfp0_lowspeed_4
BD18 - QSFP0_LPMODE_LS = qsfp0_lowspeed_0

 In our application we would need to export two IOs to SMA contacts (for generating  external pulses). That's why I would like to know if there are such IO, and if so which IO voltage domain?

At this time there is no way to use any pins for generating external pulses. 

Let me know if there's any additional clarification I can provide. 

Regards,

M

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