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Adventurer
Adventurer
905 Views
Registered: ‎06-25-2016

Alveo u200 ethernet constraints

Hi!

Can I get pin constraints for alveo u200 board? I need sys_reset, gt_ref_clk, init_clk and all lowspeed interface pins for qsfp0 and qsfp1. 

Also I want to get official project (not sdaccel) in which I can modify qsfp registers right way due to question from next post:

https://forums.xilinx.com/t5/Ethernet/Enabling-Configuring-QSFP28-module/m-p/805117

Am I need to write 93 register in qsfp in Alveo u200 through i2c fpga's port ? Or does qsfp modules turned on right way automatically in alveo?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Re: Alveo u200 ethernet constraints

Hi @slipknotchik 

I have received lots of requests in the past for pinouts but I have never received a query about writing to registers on the QSFP. 

Here is the way we've been solving this style of question in the past -

Use this link to download the Vivado constraint and board files for the u200

https://www.xilinx.com/products/boards-and-kits/alveo/u200.html#vivado 

Use this link to get the QSFP up and running 

https://www.xilinx.com/support/answers/71981.html

 

Could you let me know if this works for you? 

Regards,

M

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Adventurer
Adventurer
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Registered: ‎06-25-2016

Re: Alveo u200 ethernet constraints

Thank you! 

I've downloaded xdc file but I can't uderstand meaning of some qsfp pins in it. If I'll implement simply 100g subsystem example project from box with this xdc file without adding any pins will design work? Or am I need to add some lowspeed qsfp pins from xdc to design such as lpmode0, fs0, modskll_ls to example project?

Also I can't succeed due to your second link using block design. Automation of connections does not work good with eth subsystem  and  and I can't get output products. Second trouble is that I don't know alveo schematics and can't imagine how to set low speed signals properly. And I don't know role of i2c bus in setting of qsfp module parameters. Some vendors requires that.A I understood I don't need i2c in Alveo. Am I right?

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Adventurer
Adventurer
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Registered: ‎06-25-2016

Re: Alveo u200 ethernet constraints

And also what pin can I use as sys_clk from alveo xdc file? And what frequency is it?
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Adventurer
Adventurer
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Registered: ‎06-25-2016

Re: Alveo u200 ethernet constraints

I read about provided design files with examples and docs in ug1352. How can I download it?

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Adventurer
Adventurer
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Registered: ‎06-25-2016

Re: Alveo u200 ethernet constraints

Also one more question on u200 xdc.
What does QSFP0_FS0 and _FS1 mean? And can describe meaning of next pins: QSFP0_REFCLK_RESET, QSFP0_CLOCK_N and _P? And what direction these pins have?
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Adventurer
Adventurer
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Registered: ‎06-25-2016

Re: Alveo u200 ethernet constraints

Still all my previous questions are actual. Please do not ignore me

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Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Re: Alveo u200 ethernet constraints

Hi @slipknotchik ,

The low speed signals for the U200 / U250 Alveo cards are driven directly from the FPGA, so would need to be set via the Ethernet IP / QSFP requirements training requirements.  These are defined in the specifications for SFF QSFP ethernet, and are referenced in User Guide 1289 (Alveo U200/U250 User Guide).  Per that User Guide, these are available via I2C as well.  The I2C is available for instantiation via block automation. 

If you are having challenges with block automation specific to the Ethernet IP and connectivity requirements, I would recommend you review the Ethernet User Guide for the core you are targeting, as well post to the Ethernet forums, as they may have more specific advice.

Please review User Guide 1289 (Alveo U200/U250 User Guide) - as this has more information on the reference clocks and locations.  These should also be selectable in block automation. 

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Adventurer
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Registered: ‎06-25-2016

Re: Alveo u200 ethernet constraints

Pins QSFP0_FS0 and _FS1 and QSFP0_REFCLK_RESET, QSFP0_CLOCK_N and _P are board specific. These signals are not from SFF standart. Can you describe meaning of these signals to me?

Does FPGA has direct I2C link to QSFP? Or only BMC on Alveo have direct I2C connection to QSFP?
Also your teammate Xilinx employee said that there's no need to do anything on I2C bus from FPGA side with QSFP. Who's right?

I've had challenge with alveo block design automation. Automation was not succeed with MAC core and because of it I'm working in rtl ethernet core example project. Can you help me in that direction mostly?

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Adventurer
Adventurer
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Registered: ‎06-25-2016

Re: Alveo u200 ethernet constraints

I guess there are some i2c switches or something else between FPGA and QSFP. Can you explain me schematics of i2c bus with all multiplexing in it and base addresses of switches?

Also question on pins remains. Can you explain about pins QSFP0_FS0 and _FS1 and QSFP0_REFCLK_RESET, QSFP0_CLOCK_N and _P. What's meaning of that pins? I'm already use MGT_SI570_CLOCK_C_P and _N as gt clocking. Does that means that I don't need QSFP0_REFCLK_RESET, QSFP0_CLOCK_N and _P in design?
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Re: Alveo u200 ethernet constraints

Hi @slipknotchik 

I'm trying to get you some more answers to your questions. I don't think I2C is the way to go, and we do not have I2C register definitions or schematics to provide.

If I'll implement simply 100g subsystem example project from box with this xdc file without adding any pins will design work?

Probably not. The example projects are not board aware and they do not inherit the board file information from the board files. You could use the XDC but you'd need to set all the IPs and clocks correctly. The best way for you to determine what the IP configuration should be would be starting with an IPI design and using those settings as a reference. There's also a matter of the XDC pin names aren't always obvious. 

Or am I need to add some lowspeed qsfp pins from xdc to design such as lpmode0, fs0, modskll_ls to example project?

lpmode0 should be 0

Also I can't succeed due to your second link using block design. Automation of connections does not work good with eth subsystem  and  and I can't get output products.

So unfortunately, where we are at with the GT reference designs and what is required to get Ethernet IP working we don't have additional reference material. Should be coming soon and I understand your frustration. For example, there is no way to connect the LBUS interface to anything in IPI, so you'd need to use the AXI streaming interface. 

And also what pin can I use as sys_clk from alveo xdc file? And what frequency is it?
You should have a board, preset, and pins . xml files these will tell you the frequency of the clocks and how to configure the IP as well. 
Sys_clk is 300 mhz, we use a clock block to change that to 100Mhz to drive the init. You need to also drive the drp clock from a free running clock, you can use that same 100MHz clock. 
GT ref clock input to the CMAC comes from the QSFP and can only be 156.25 MHz

I read about provided design files with examples and docs in ug1352. How can I download it?

https://github.com/Xilinx/Get_Moving_With_Alveo

I made a quick and ugly block diagram with a CMAC using the board flow, then I generated a wrapper for this block so that you can use it in a RTL design. 

I don't know if this will work but it should get you unstuck for now. image.pngimage.png

 

 
What does QSFP0_FS0 and _FS1 mean? And can describe meaning of next pins: QSFP0_REFCLK_RESET, QSFP0_CLOCK_N and _P? And what direction these pins have?
Looking for this information. Not sure if you need to use it if you instead use the board aware flow and a similar block above as these are not pins in the XML files. 
 
The user guide says this:
The QSFP+ connectors are accessible via the I2C interface on the Alveo U200/U250 accelerator
cards. The QSFP connector’s sideband signals are accessible directly from the FPGA. The
MODSELL, RESETL, MODPRSL, INTL, and LPMODE sideband signals are defined in the small
form factor (SFF) specifications listed below.
For additional information about the quad SFF pluggable (28 Gb/s QSFP+) module, see the
SFF-8663 and SFF-8679 specifications for the 28 Gb/s QSFP+ at the SNIA Technology Affiliates
website: https://www.snia.org/sff/specifications2.
 
But that link doesn't work, so I had to look up SFF-8663 and SFF -8679 on google. 
I'm looking for direct answers to how to drive the low speed signals, but again since Xilinx doesn't currently offer a product/application that uses the QSFPs there may not be additional reference material available. 
 
Possibly the linked document will give you enough information to drive the QSFP low speed signals. 
 
Regards,
M
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Adventurer
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Registered: ‎07-27-2018

Re: Alveo u200 ethernet constraints

Hi @mcertosi 

sorry if i get the discussion now,

I'm delevoping 100G on VCU1525, I read your last post in particular:

"Or am I need to add some lowspeed qsfp pins from xdc to design such as lpmode0, fs0, modskll_ls to example project?

lpmode0 should be 0"

The specification you linked cites:

5.3.3 LPMode/TxDis
LPMode/TxDis is a dual-mode input signal from the host operating with active high
logic. It shall be pulled towards Vcc in the module. At power-up or after ResetL is
deasserted LPMode/TxDis behaves as LPMode. If supported, LPMode/TxDis can be
configured as TxDis using the two-wire interface except during the execution of a
reset. TxDis provides an optional fast mode, see definition in SFF-8636.
When LPMode/TxDis is configured as LPMode, the module behaves as though TxDis=0. By
using the LPMode signal and a combination of the Power_override, Power_set and
High_Power_Class_Enable software control bits (SFF-8636, Address A0h, Byte 93 bits
0,1,2), the host controls how much power a module can consume. See section 5.6 for
more details on the power supply specifications.
When LPMode/TxDis is configured as TxDis, the module behaves as though LPMode=0.
In this mode LPMode/TxDis when set to 1 or 0 disables or enables all optical
transmitters within the times specified in Table 8-2.

 

Now the document says LPmode have to be set to Vcc not to 0, in this case you have Tx enabled

but at the lower trasmission power (that is 1.5W).

From the specification it is not enough to set LPMode to zero if you don't set the pin to function as TxDis.

In case you set the pin as TxDis by I2C, LPMmode = 0 will enable the trasmission.

Does Xilinx set this pin like TxDis at boot time by I2C?

 

Just for example in the VCU1525 the schematic pulls the LPMode pin to Vcc (UG1268 v1.0)

Best Regards

 

 

 

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