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puya
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Registered: ‎11-20-2018

Alveo (u200, u250) XOCC failes in implementaion due to delay file mismatch!

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Hi,

I am using xocc to link a xo file, synthesis and implement the system. but the process fails with this error in log file:

INFO: [VPL 17-86] Your Implementation license expires in 14 day(s)
ERROR: [VPL 35-513] External delay file revision does not match speed controllers revision
Speed Controller: PRODUCTION 1.26 06-20-2019
External File: PRODUCTION 1.23 03-18-2019

I am using the last Deployment and Development Shells for ubuntu 18.04

I tried it with both U200 and U250 platform

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puya
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Registered: ‎11-20-2018

Fixed by installing the November update of Vitis.

**** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
**** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019

View solution in original post

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puya
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Registered: ‎11-20-2018
I could generate the the xclbin file for Alveo U280 accelerator. It seems the Development Shells for other cards are not compatible with the last version of SDAccel. Anyone to confirm it?
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mcertosi
Xilinx Employee
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Registered: ‎10-19-2015

Hi @puya 

I don't expect this behavior. Are you using 2019.1?

Can you tell me which u200 and u250 shells you were testing with? 

I'd like the full file name, as that contains the version number in it.

Can you point me to the example project you are generating? 

Regards,

M

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puya
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HI @mcertosi

Yes I use SDAccel 2019.1

Fot XRT, I just cloned the master branch and compiled it as I could not install the available deb package for ubuntu 18.04.

U200:

xilinx-u200-xdma-201830.2-2580015_18.04.deb
xilinx-u200-xdma-201830.2-dev-2580015_18.04.deb

u250:

xilinx-u250-xdma-201830.2-2580015_18.04.deb
xilinx-u250-xdma-201830.2-dev-2580015_18.04.deb

u280:

xilinx-u280-xdma-201910.1-2579327_18.04.deb
xilinx-u280-xdma-dev-201910.1-2579327_18.04.deb

I am not using Xilinx examples. I am trying SDAccel for a box filter kernel which is auto-generated by a particular compiler, so the code might not be human-readble but you can check the interface pragmas if it is needed. The code is available at:

https://github.com/pooyaww/AnyHLS_SDx/tree/master/SDAccel/box_filter_ocl

Everything get fully implemented on U280 with a minor bug which is exporting locale variable: export LC_ALL="C"

Regards,

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mcertosi
Xilinx Employee
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Registered: ‎10-19-2015

Hi @puya 

The problem looks specific to this kernel. Can you give me the exact steps how to build the github project you pointed me to? I'd also like the exact steps on how to reproduce your problem. 

 

If that's not possible, try building one of the sdaccel example projects to verify that the u20 and u250 work with the 2019.1 SDAccel tool. 

Regards,

M

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puya
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@mcertosi

I can provide you with the build instructions for my kernel but as you suggested I rebuilt one of the SDAccel examples named "systolic_array_c ":

https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/kernel_opt/systolic_array_c

The problem appears only if I ask for implementation , using TARGET=hw . So it seems the problem is not particular to my kernel.

Let me know if any more information is required.

As far as I compile for emulation by TARGET=sw_emu or TARGET=hw_emu, the building process is successful.

Regards,

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mcertosi
Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Hi @puya 

Can you tell me about how far into the build the build fails with the error message from the first post? 

I can't seem to reproduce this problem with the 2019.1 SDAccel tool and the xilinx_u250_xdma_201830_2.

It is possible that the DSA  was generated in a version of the tools that had a different speedfile. I think you already have but, can you double check you are using the latest U200 and U250 DSAs from Xilinx.com? 

https://www.xilinx.com/products/boards-and-kits/alveo/u200.html#gettingStarted

https://www.xilinx.com/products/boards-and-kits/alveo/u250.html#gettingStarted

Regards,

M

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puya
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Hi @mcertosi 

I reinstalled the DSA and platforms for U200 from those links you sent again, and rebuilt that example. still the same problem exists.

I copied whatever is printed on the terminal. you can find it in the following link.

https://pastebin.com/S7T05Bec

Best,

 
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mcertosi
Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Hi @puya 

What is the error in the implementation log from the make's output?

ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, place_design ERROR, please look at the run log file '/home/puya/Documents/Snippets/HLS/X_SDAccel/SDAccel_Examples/getting_started/kernel_opt/systolic_array_c/_x.hw.xilinx_u200_xdma_201830_2/mmult/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information

Maybe there is something in your tool's configuration is doing something unexpected. Can you send me the output or a screenshot from Help > About Xilinx SDx, click Installation Details, then go to Configuration. This shows pretty much everything about the Eclipse setup, minus environment variables. 

Regards,

M

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puya
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Hi @mcertosi 

I attached both requested files and also a print of all environment variables of the same terminal I built the project with.

Regarding the log file I see no more information than the same speedfile error.

Regards,

 

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giulioc
Xilinx Employee
Xilinx Employee
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Registered: ‎05-20-2010

Hi, 

I think I solved for my case increasing the swap file, it can be worth for you trying. I target the U200

I had a very similar inexplicable error even with the helloworld example. Example is:

https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/hello_world.

Error has been

[09:06:02] Run vpl: Step impl: Failed
[09:06:08] Run vpl: FINISHED. Run Status: impl ERROR
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, place_design ERROR, please look at the run log file '/media/giulioc/TerabyteHD/Alveo/SDAccel_Examples/getting_started/hello_world/helloworld_c/_x.hw.xilinx_u200_xdma_201830_2/vadd/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [XOCC 60-1442] [09:06:15] Run xocc_link: Step vpl: Failed
Time (s): cpu = 00:00:15 ; elapsed = 00:19:48 . Memory (MB): peak = 644.418 ; gain = 0.000 ; free physical = 7751 ; free virtual = 8285
ERROR: [XOCC 60-661] xocc link run 'xocc_link' failed
ERROR: [XOCC 60-626] Kernel link failed to complete
ERROR: [XOCC 60-703] Failed to finish linking
Makefile:89: recipe for target 'xclbin/vadd.hw.xilinx_u200_xdma_201830_2.xclbin' failed
make: *** [xclbin/vadd.hw.xilinx_u200_xdma_201830_2.xclbin] Error 1

 

I made the swapfile larger from 2 Gigabytes to 12 Gigabytes see below.

 

=====================

~$ sudo -i

~# swapon --show

NAME TYPE SIZE USED PRIO
/swapfile file 2G 13M -2

~# swapoff -a

~# sudo fallocate -l 12G /swapfile

~# chmod 600 /swapfile

~# mkswap /swapfile

mkswap: /swapfile: warning: wiping old swap signature.
Setting up swapspace version 1, size = 12 GiB (12884897792 bytes)
no label, UUID=d8d378fc-98e1-4cf8-a5ec-8cea622dde0f

~# swapon /swapfile

~# gedit /etc/fstab

I put in this statement for permanent swapfiel :    /swapfile swap swap defaults 0 0

and saved the file. Now the swapfile is permanent.

~# swapon --show
NAME TYPE SIZE USED PRIO
/swapfile file 12G 0B -2

Now with 12G of swap it worked

Result after increasing swap fileResult after increasing swap file

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puya
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Registered: ‎11-20-2018

Hi @giulioc 

I did what you suggested. I increased the swap file to 12G while my workstation has 64G RAM.

But nothing changed.

puya@rocky:~$ swapon --show
NAME TYPE SIZE USED PRIO
/swapfile file 12G 0B -2

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puya
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Registered: ‎11-20-2018

Fixed by installing the November update of Vitis.

**** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
**** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019

View solution in original post

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