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Explorer
Explorer
585 Views
Registered: ‎06-14-2018

Bandwidth problem on Alveo 200

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Hi,

I can't get more than 710MB/s global/kernel kernel/global on an Alveo cloud solution.

Using burst make things worse.

Is it a known behavior ?

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Xilinx Employee
Xilinx Employee
505 Views
Registered: ‎12-10-2013

Re: Bandwidth problem on Alveo 200

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That is definitely what it looks like.  If there is another card on the same switch, it is possible you are getting split bandwidth.  Assuming this is a cloud application, I don't know that you will have much control over the host topography. 

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8 Replies
Explorer
Explorer
574 Views
Registered: ‎06-14-2018

Re: Bandwidth problem on Alveo 200

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Actually, the data path evaluated here is host->global->fpga->global->host, without any fpga treatment.

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Xilinx Employee
Xilinx Employee
544 Views
Registered: ‎12-10-2013

Re: Bandwidth problem on Alveo 200

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Hi @xil_tour ,

What kind of bandwidth is xbutil validate seeing?

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Explorer
Explorer
526 Views
Registered: ‎06-14-2018

Re: Bandwidth problem on Alveo 200

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This is the output:

INFO: Found 1 cards

INFO: Validating card[0]: xilinx_u200_xdma_201830_1
INFO: Checking PCIE link status: PASSED
INFO: Starting verify kernel test: 
INFO: verify kernel test PASSED
INFO: Starting DMA test
Host -> PCIe -> FPGA write bandwidth = 5222.26 MB/s
Host <- PCIe <- FPGA read bandwidth = 3227.9 MB/s
INFO: DMA test PASSED
INFO: Starting DDR bandwidth test: ..........
Maximum throughput: 47853.664062 MB/s
INFO: DDR bandwidth test PASSED
INFO: Card[0] validated successfully.

INFO: All cards validated successfully.
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Explorer
Explorer
522 Views
Registered: ‎06-14-2018

Re: Bandwidth problem on Alveo 200

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A second try:

INFO: Found 1 cards

INFO: Validating card[0]: xilinx_u200_xdma_201830_1
INFO: Checking PCIE link status: PASSED
INFO: Starting verify kernel test: 
INFO: verify kernel test PASSED
INFO: Starting DMA test
Host -> PCIe -> FPGA write bandwidth = 11303.6 MB/s
Host <- PCIe <- FPGA read bandwidth = 12193.1 MB/s
INFO: DMA test PASSED
INFO: Starting DDR bandwidth test: ..........
Maximum throughput: 47404.167969 MB/s
INFO: DDR bandwidth test PASSED
INFO: Card[0] validated successfully.

INFO: All cards validated successfully.

The Alveo 200 is a Gen3x16 PCIe.

So the max attainable is 15,754 Go/s

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Explorer
Explorer
519 Views
Registered: ‎06-14-2018

Re: Bandwidth problem on Alveo 200

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Third try:

INFO: Found 1 cards

INFO: Validating card[0]: xilinx_u200_xdma_201830_1
INFO: Checking PCIE link status: PASSED
INFO: Starting verify kernel test: 
INFO: verify kernel test PASSED
INFO: Starting DMA test
Host -> PCIe -> FPGA write bandwidth = 9895.56 MB/s
Host <- PCIe <- FPGA read bandwidth = 10839.1 MB/s
INFO: DMA test PASSED
INFO: Starting DDR bandwidth test: ..........
Maximum throughput: 48073.222656 MB/s
INFO: DDR bandwidth test PASSED
INFO: Card[0] validated successfully.

INFO: All cards validated successfully.

Could it be that I'm not alone on the PCIe ?

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Xilinx Employee
Xilinx Employee
506 Views
Registered: ‎12-10-2013

Re: Bandwidth problem on Alveo 200

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That is definitely what it looks like.  If there is another card on the same switch, it is possible you are getting split bandwidth.  Assuming this is a cloud application, I don't know that you will have much control over the host topography. 

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Explorer
Explorer
439 Views
Registered: ‎06-14-2018

Re: Bandwidth problem on Alveo 200

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Here's the bandwith per quantity of data.

I'm using xbutil dmatest, only using the top 5 values average over 1200 tests :

image-avg_top5.png
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Explorer
Explorer
432 Views
Registered: ‎06-14-2018

Re: Bandwidth problem on Alveo 200

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