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Contributor
Contributor
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Registered: ‎05-04-2020

Can I have access to PCIe on SDAccel/Vitis OpenCL solution

I have made a application for Alveo U200 by using OpenCL. After compilation, I can see the RTL code for the kernel and its interfaces by looking into the Vivado project. However, I was wondering if there is any way that I can see the block design of the whole system that is going to be programmed on the FPGA board and edit that. I mean, I need to have access not only to the kernel RTL but I need access to other static IPs, such as PCIe that used for communication. I think these stuff are linked afterward to build xclbin. 

Why do I want to do this: I have two modules where each of them use the PCIe and I want them on the same FPGA board, sharing the PCIe. I've implemented one of them with OpenCL. I implemented the other one in RTL which uses PCIe as well. I want to integrate this RTL IP into the OpenCL project and directly connect it to the PCIe to occasionally pause the other module and send raw TLPs to the PCIe port. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Re: Can I have access to PCIe on SDAccel/Vitis OpenCL solution

Hi @nzh 

The recommended flow would be to remove PCIe from your RTL block, then use the RTL kernel wizard in Vitis to create a kernel. Then the Vitis V++ compiler would connect you to the same PCIe block as the one used in your openCL code. 

During V++ build and linking you can specify that you want to use 2 kernels and the tool should take care of the rest. 

See this part of the documentation. Once you have your kernels in XO files, then it is easy to connect them. 

To answer your direct question, you can view the Block Diagram of the XCLBIN in Vivado, but you cannot edit it. 

Regards,

M

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Contributor
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Registered: ‎05-04-2020

Re: Can I have access to PCIe on SDAccel/Vitis OpenCL solution

@mcertosithanks for the reply.


To answer your direct question, you can view the Block Diagram of the XCLBIN in Vivado, but you cannot edit it. 

When I open the Vivado project from Vitis, this is what I see:

Screenshot from 2020-05-26 17-39-09.png

Is this the XCLBIN? I don't see the PCIe, XDMA IPs or any connection to them. 


See this part of the documentation. Once you have your kernels in XO files, then it is easy to connect them. 


sorry I don't see a link. which documentation should I look at?


@mcertosi wrote:

Hi @nzh 

The recommended flow would be to remove PCIe from your RTL block, then use the RTL kernel wizard in Vitis to create a kernel. Then the Vitis V++ compiler would connect you to the same PCIe block as the one used in your openCL code. 


But by starting an RTL block I have to follow the interface that is generated, when I remove the PCIe IP and add it to the RTL block how can I have connections to the PCIe IP? This module is going to send raw tlp packets to the PCIe IP and doesn't go through DMA.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Re: Can I have access to PCIe on SDAccel/Vitis OpenCL solution

Hi @nzh 

Sorry I forgot the link to our kernel programming model - https://www.xilinx.com/html_docs/xilinx2019_2/vitis_doc/Chunk2086915788.html

"But by starting an RTL block I have to follow the interface that is generated, when I remove the PCIe IP and add it to the RTL block how can I have connections to the PCIe IP? This module is going to send raw tlp packets to the PCIe IP and doesn't go through DMA."

Ah, interesting, you can't do that in Vitis, you need to use a DMA. What is the endpoint of the tlp packets? 
Regards,
M
 
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Contributor
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Registered: ‎05-04-2020

Re: Can I have access to PCIe on SDAccel/Vitis OpenCL solution

@mcertosi  The TLP packets just read some predefined "physical address" in the host memory and do some processing on them. Unfortunately, we can't change the way that this module works and we need to just integrate it into Vitis module.  

Could you please tell me if the block diagram that I sent in the previous message is the whole xclbin? then where is the DMA and PCIe IP in the diagram? or how is it connected to them?  

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Re: Can I have access to PCIe on SDAccel/Vitis OpenCL solution

Hi @nzh 

I can't tell in the last image if you are looking at the full xclbin. The xclbin would include ddr, DMA, and PCIe so if you see those and you compiled in Vitis then yes. 

Maybe you want to make another PCIe physical function that the tlp packet can communicate with directly? I think this would take you out of the Vitis flow though. 

I don't think there is a way to remove the DMA from PCIe in Vitis. 

Regards,

M

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Contributor
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Registered: ‎05-04-2020

Re: Can I have access to PCIe on SDAccel/Vitis OpenCL solution


@mcertosi wrote:

I can't tell in the last image if you are looking at the full xclbin. The xclbin would include ddr, DMA, and PCIe so if you see those and you compiled in Vitis then yes. 


@mcertosi That's exactly my problem. I compiled vector_add example in Vitis and then opened the Vivado project from the menu and this is what I see. I can't see how this is the xclbin because I don't see dma and pcie IPs in this diagram and where are the connections to PCIe? What am I missing here?

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Re: Can I have access to PCIe on SDAccel/Vitis OpenCL solution

Hi @nzh 

PCIe should be in the SLR1 block, please expand that and continue looking. 

Regards,

M

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