03-26-2020 09:13 PM
I would like to know is there a way to lower the DDR4 frequency from the default speed rating of 1200 to 800?
I tried to change the "Memory Device Interface Speed (ns)" setting in Vivado, but it seems fixed at 833.
03-27-2020 12:05 PM
The DDR4 interface speeds are fixed for the acceleration flow.
Are you using a Vitis platform for the u250 or doing something else?
03-29-2020 08:46 PM
No, I am not using the Vitis platform. I have been using Vivado for top level Xilinx components instantiation and stitching, and using Vivado to constrain the design.
I don't have any experience using the Vitis platform, will I be able to change the DDR clock frequency if I use the Vitis platform?
03-30-2020 11:05 AM
In the acceleration flow / platform usage you can change the kernel clock. There is automatic clock crossing logic that is then inserted from the user/kernel clock.
If that clock crossing logic is handled for you, why would you want to decrease the frequency of the DDR4?
03-30-2020 06:16 PM
The reason why I want to lower the DDR clock frequency is that my FPGA tests tend to fail more if the ratio of the engine clock to the DDR clock is high. I want my FPGA tests to fail more often which would help root cause the problem in my logic. Cranking up the frequency of the engine clock results in lengthy P&R time, so I was hoping I can reduce the DDR clock frequency without changing the engine clock frequency.
I am confused, so you were saying it is possible to change the DDR clock frequency, either through Vivado or Vitis?
03-31-2020 11:05 AM
I see somewhat of what you are doing. This isn't standard and cannot be done in the standard flow.
I apologize, it would likely be the best path forwards to replace and route to change your engine's operating frequency.