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Visitor
Visitor
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Registered: ‎11-06-2019

Custom 10G ethernet subsystem for Alveo U250

I would like to design a custom 10G Ethernet subsystem for Alveo U250. I should focus on decreasing latency (make it as small as possible) while designing the IP Core. The problem is I only have a year of small FPGA experience (Intel cyclone 5 SoC, comparable to Zynq 7000 SoCs). 

I have coded with Verilog, created some basic IP's, have basic knowledge about IPv4 ( I only know ARP data structure well at this point). 

Obviously, there are many things I have to learn to be able to achieve my goal (need to have deep knowledge of transceivers on Alveo U250, AXI4, IPv4 protocols, timing, etc.). 

What are the steps I should take? 

Are there any set of tutorials and documents you highly recommend?

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Explorer
Explorer
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Registered: ‎06-28-2018

Re: Custom 10G ethernet subsystem for Alveo U250

This repo has 10G Ethernet components written in Verilog

https://github.com/alexforencich/verilog-ethernet