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upside_down
Visitor
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Registered: ‎11-06-2019

Detailed Hardware and I/O pins documentation for Alveo U250

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Hello,

We are considering to use Alveo U250 to implement our custom RTL design/architecture. Many commonly used FPGA boards contain a detailed information about their I/O pins, transceiver locations, which pins are connected to specific ports, etc. I attached the example document for VCU118 board. Does a similar document for Alveo U250 exist? If yes, I would be happy if anyone could help me find it. If the answer is NO, what should I do if I want to implement custom RTL design on it? 

Also which Vivado versions support Alveo U250 as a TDP (Target design platform)?  

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bethe
Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Hi @upside_down 

For a custom PCS/PMC + MAC IP core, you would definitely need to go the Custom Flow route, as GTs in the dynamic region of accelerated flow does not yet have a target support date.

The XDC needed to hook up to the GTs is provided in Vivado as part of the Board Aware Flow, and the QSFP pins, to the extent provided are in UG1289.   That being said, the Custom Flow with Alveo U250 is really targeted at the customers who are very experienced in FPGA and hardware design on our products, and the hardware, as a production board, is fairly locked down.  For example, on the development boards, we provide assistance in changing the reference clocks, but on Alveo, they are fixed.  For many of the development boards, we also have reference designs that can be leveraged as a starting place, which is not something provided on the Alveo cards.

I have seen customers successfully design Ethernet to PCIe on U250, but it is definitely a route only recommended to very experienced users.   If you are evaluating the Xilinx technology and will need significant assistance / support / examples, then I would highly recommend starting on one of the development cards vs. the production Alveo cards. 

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drjohnsmith
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Registered: ‎07-09-2009

I havnt used it, and am interested in the official responce,

   but from what I remember of the presentations, this card is not an eval board , its a product,

https://www.xilinx.com/products/boards-and-kits/alveo/u250.html#gettingStarted

https://empa.com/dokumanlar/pts/Alveo_Product_Overview.pdf

The dfference is that Xilinx expect you to use the supplied interface code and not get down to the nitty grity of the board. 

https://www.xilinx.com/support/documentation/boards_and_kits/accelerator-cards/ug1289-u200-u250-reconfig-accel.pdf

https://www.xilinx.com/support/documentation/boards_and_kits/accelerator-cards/2019_2/ug1301-getting-started-guide-alveo-accelerator-cards.pdf

 

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bethe
Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Hi all,

 

@drjohnsmithis correct.  The Alveo Data Center Accelerator cards are a production environment hardware platform and are not a development card.  There are two different paths to using the Alveo card:

1) Acceleration Flow - tested, supported, characterized.  Available tool set, drivers, APIs, OpenCl (for those wanting to use it) - accessed through the HW Development Platforms and Vitis tool.  Xilinx provides a HW Platform, which includes a network of PCIe connectivity, Memory (DDR or HBM), dynamic AXI infrastructure, card management, and allows you to load in an "xclbin" - a partial reconfiguration bistream that does the hardware acceleration - and can be swapped out.  The host code assists in this.  A user design can be RTL, OpenCL, or several other variants.  This is very much the recommended flow as the infrastructure to recreate much of the card interaction is very difficult.   There are firewalls, management paths, DMA data paths - all designed and optimized.

2) Custom Flow - This is a bit more like what you are describing with a VCU118, but since Alveo is not a development board, much, much more of the hardware is locked down and not adjustable.  The UG1289 (for U200 / U250) is an example of the information we provide, along with the board files for 'board aware flow' in Vivado.   If the information is not there, or the ports / access is not described, then that is not something we are releasing nor will be available through technical support as "additional information".   While this 'flow' is more familiar to the tradional FPGA Development board user, that is not the intent of the Alveo product.  

As an observation through the last year+ since product go-live, I have seen folks go both directions.   The time-to-market success is definitely on the Accelerated path, as learning the new tool set and getting to leverage all the existing infrastructure and support is shorter ramp than starting from scratch.  A common reason I have heard from customers for going custom is the size of the HW Platform, but once we have gotten into the design and features folks find it is very optimized for what you get, and recreating the architecture, you end up in the same ballpark.   If you are a "load it once, deploy it in the field, and never touch again" there may be a value proposition then.  But if you are looking for long term, multiple use acceleration, with field updates and infrasture - Acceleration Vitis flow is really the right investiment of time.

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upside_down
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Registered: ‎11-06-2019

@bethe, thanks for the reply

Actually we want to design a system that gets information from network (using GTY transceivers through QSFP28). We need to design a custom PCS/PMA + MAC IP Core and custom RTL logic which will be used to work on data received through transceivers, and communicate with CPU through PCIe Gen3. The custom RTL logic will use all available on chip memory blocks. Currently, we are unable to design a custom FPGA board, so we needed to choose one of the available FPGA boards (with a Virtex Ultrascale+ FPGA) on market. 

We were considering to use an Alveo board, as it is commonly used, popular, easier to get, relatively cheap, etc. As U250 has the most available on chip memory among the members of Alveo family, we considered to use Alveo U250 for our product. 

We do not know what has changed since then, but according to June 28, 2019 (v1.1) version of the ds962 (U200 and U250 datasheet, Table 7), total of 1280 288Kb UltraRAMs, 2000 36Kb block RAMs and 2749K registers are available in dynamic region of the XCU250 FPGA. If it was possible to fully program the Alveo U250 board (the XCU250 FPGA), there would be enough on chip memory resource for us, or even if we could program only the dynamic region of the device, it would be enough for now. 

Of course to be able to implement our design on U250, we will need some hardware/architecture information, XDC file, and some support (for RTL design on U250). And I want you to know that (to get better answer) we are using Xilinx Ultrascale+ for the first time, so currently we do not know what kind of difficulties are waiting for us if we decide to use U250 at this stage.

Now you have more information to be able to give us a better answer.

 

  1. Do you recommend us to use Alveo U250 at this stage? 
  2. If we choose the "Custom Flow", is it better to use the U250, or try to find another Virtex Ultrascale+ board with similar capabilities?
  3. If we choose the "Acceleration Flow", is it possible to integrate our custom RTL system designed using Verilog HDL (the custom PCS/PMA + MAC IP Core and custom RTL logic) with Alveo U250 standard logic ("Static Region")?

It would be nice if you could help us to make better decision.

Thanks

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bethe
Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Hi @upside_down 

For a custom PCS/PMC + MAC IP core, you would definitely need to go the Custom Flow route, as GTs in the dynamic region of accelerated flow does not yet have a target support date.

The XDC needed to hook up to the GTs is provided in Vivado as part of the Board Aware Flow, and the QSFP pins, to the extent provided are in UG1289.   That being said, the Custom Flow with Alveo U250 is really targeted at the customers who are very experienced in FPGA and hardware design on our products, and the hardware, as a production board, is fairly locked down.  For example, on the development boards, we provide assistance in changing the reference clocks, but on Alveo, they are fixed.  For many of the development boards, we also have reference designs that can be leveraged as a starting place, which is not something provided on the Alveo cards.

I have seen customers successfully design Ethernet to PCIe on U250, but it is definitely a route only recommended to very experienced users.   If you are evaluating the Xilinx technology and will need significant assistance / support / examples, then I would highly recommend starting on one of the development cards vs. the production Alveo cards. 

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