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s.corda
Observer
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Registered: ‎02-27-2019

HBM axi width

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Hi,

I have some questions regarding the HBM on the Alveo u50:

 

Thanks

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JohnFedakIV
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Registered: ‎09-04-2020

Hi @s.corda,

The U50 is power limited for the HBM (it is powered by the 10W PCIe 3.3V supply), while the U280 is not - so this may be why the examples utilize different number of channels.

For the first and third questions, I would take a look at these 2 topics:
https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/Questions-about-HBM-bandwidth/td-p/1166085
https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/Questions-about-reading-data-from-HBM/td-p/1167283

Regards,
~John

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JohnFedakIV
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Registered: ‎09-04-2020

Hi @s.corda,

The U50 is power limited for the HBM (it is powered by the 10W PCIe 3.3V supply), while the U280 is not - so this may be why the examples utilize different number of channels.

For the first and third questions, I would take a look at these 2 topics:
https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/Questions-about-HBM-bandwidth/td-p/1166085
https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/Questions-about-reading-data-from-HBM/td-p/1167283

Regards,
~John

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s.corda
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Registered: ‎02-27-2019

Hi @JohnFedakIV,

Thanks for your reply!

Regarding the first question I am checking your answer here: https://forums.xilinx.com/t5/Alveo-Accelerator-Cards/HBM-bandwidth-example/td-p/1226868

For question 2 and 3, I have already checked those posts. It seems that the HBM axi interface is 256 bits and the maximum axi kernel interface is 512 bits. However, I see that in the HBM bandwidth example (https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/host/hbm_bandwidth) it is used float16, which is 512 bits. Am I missing something? 

 

Regards,

Stefano

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JohnFedakIV
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Registered: ‎09-04-2020

Hi @s.corda ,

I checked with the team that created the examples - the HBM bandwidth kernel does use a 512 bit bus, this is because the HBM works on a higher frequency than the programmable logic fabric.

As mentioned in the HBM Product Guide (PG 276), the AXI3 protocol runs at 450MHz. On the other hand, User Kernel typically runs in the range of 250MHz to 300MHz (depending on Kernel critical path). As a result, a 512bit M_AXI kernel design is designed to saturate all of 256bit AXI3 running @450MHz.

Regards,
~John

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s.corda
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Registered: ‎02-27-2019

Hi @JohnFedakIV,

Thanks for the explanation. In this scenario it makes sense.

In the case I have a kernel running at 400 MHz (compiled with --kernel-frequency 400). Should I use 256bits and then match the HBM clock frequency?

In this work https://arxiv.org/pdf/2010.00289.pdf the kernel frequency is increased with Vitis at 450MHz using a 512bits AXI.

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JohnFedakIV
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Registered: ‎09-04-2020

Hi @s.corda ,

It may become hard to meet timing requirements at these higher frequencies with a full system design. In either case (512bit at lower frequency or 256bit at the same HBM frequency) , you will be saturating the HBM AXI bandwidth and with the U50, running into the 10W limit.

Regards,
~John

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