04-08-2020 08:24 PM
Like the picture shows, I am trying to make the hbm to be accessed by both host and the fpga logic.
With a axi interconnect module, the host access the hbm from the qdma by axi mm interface, and the logic side i tried to access the hbm stll by axi ports, but there is a problem that the axi interconnect module can only be configurated to 1 slave interface, if the number of slave interfaces is greater than 1, the maximal master interfaces is 16, which is less than the necessary number of 32 master interfaces for the hbm core.
So will it is possbile to make the hbm as shared memorys, is there any other modules to achieve this？
Thanks a lot.
04-14-2020 08:24 AM
The HBM comes with an AXI switch that allows any of the Slave ports to access any of the Pseudo Channel memory spaces.
Could you use this feature to achieve what you are trying to do?
See this document as a reference for the HBM. See the information on page 14, and how to enable global addressing starting on page 20.