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ericleaf
Observer
Observer
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Registered: ‎10-08-2018

How to connect to the xdma/ddr4 IP (in static region) in Vivado block design?

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Hi,

I'm using Alveo U250 board. I want to understand how can I connect my RTL accelerator to the xdma/ddr4 IP (in static region) in Vivado block design?

Specifically, I want to connect an AXI-Lite slave interface to xdma, and an AXI4 master interface to ddr4. More generally, how can I get all the interfaces provided by the static region, in a way like the PS IP in ZYNQ?

Thanks.

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mcertosi
Xilinx Employee
Xilinx Employee
868 Views
Registered: ‎10-19-2015

Hi @ericleaf 

Thanks for the clarification. Your needs will be met by using a shell (static region) provided by Xilinx and using an RTL kernel. The way the RTL kernel is implemented is up to you, as you are welcome to generate your RTL kernel files outside of SDAccel as well as with the help of SDAccel. For beginners we recommend checking out the getting started examples as well as using the RTL kernel wizard in SDAccel.

Also, the shell comes with a test program that you can run by typing $xbutil validate after sourcing XRT. 

Do you have XRT installed and set up? 

XRT is our run time environment and is designed for interacting with our accelerator cards.

I do not recommend using the Vivado integrator flow, but I also don't want to leave your questions unanswered 

You can still access the DDRs in the Vivado flow, you'd place the DDR down in the design and connect your acceleration kernel to it. The distinction here is one of semantics, there is no static region in the Vivado flow because you are not implementing a partial reconfigurtaion design. In a sense the whole design is the static region since you can't use XRT to change and reprogram the design. This is in contrast to the SDAccel flow where you can have multiple .xclbins available and load them over PCIe with the $xbutil command. This is nice since you do not need a JTAG cable or physical presence at the card. 

Regards,

M

 

Edit* changed the RTL Kernel Wizard reference to the 2019.1 guide

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mcertosi
Xilinx Employee
Xilinx Employee
910 Views
Registered: ‎10-19-2015

Hi @ericleaf 

Can you clarify if you are trying to use SDAccel and XOCC to integrate your RTL accelerator into the Alveo card OR looking to build a design using Vivado IP integrator only using the flow documented in this AR? 

The answers are quite different, you mentioned the static region which is specific to the SDAccel flow, you also mentioned connecting your RTL accelerator to the DDR4 IP using Vivado IPI which is specific to the flow in AR# 71754.

Regards,

M

 

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ericleaf
Observer
Observer
887 Views
Registered: ‎10-08-2018

Hi, @mcertosi:

Thanks very much for your reply. Basically, I'm just trying to make my accelerator be able to communicate with PCIe and DDR. So both Vivado IP Integrator flow OR SDAccel flow is okay.

I'm not familiar with SDAccel. I checked the user guide of SDAccel and found I can integrate RTL design into SDAccel flow. I believe this solution works for me. Thanks!

You mentioned there is no static region in the Vivado IP Integrator flow, right? If this means I actually cannot access PCIe and DDR in the Vivado IP Integrator?

Best Regards

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mcertosi
Xilinx Employee
Xilinx Employee
869 Views
Registered: ‎10-19-2015

Hi @ericleaf 

Thanks for the clarification. Your needs will be met by using a shell (static region) provided by Xilinx and using an RTL kernel. The way the RTL kernel is implemented is up to you, as you are welcome to generate your RTL kernel files outside of SDAccel as well as with the help of SDAccel. For beginners we recommend checking out the getting started examples as well as using the RTL kernel wizard in SDAccel.

Also, the shell comes with a test program that you can run by typing $xbutil validate after sourcing XRT. 

Do you have XRT installed and set up? 

XRT is our run time environment and is designed for interacting with our accelerator cards.

I do not recommend using the Vivado integrator flow, but I also don't want to leave your questions unanswered 

You can still access the DDRs in the Vivado flow, you'd place the DDR down in the design and connect your acceleration kernel to it. The distinction here is one of semantics, there is no static region in the Vivado flow because you are not implementing a partial reconfigurtaion design. In a sense the whole design is the static region since you can't use XRT to change and reprogram the design. This is in contrast to the SDAccel flow where you can have multiple .xclbins available and load them over PCIe with the $xbutil command. This is nice since you do not need a JTAG cable or physical presence at the card. 

Regards,

M

 

Edit* changed the RTL Kernel Wizard reference to the 2019.1 guide

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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ericleaf
Observer
Observer
845 Views
Registered: ‎10-08-2018

Hi @mcertosi

Thanks for your reply. I think SDAccel flow will work for me.

Best Regards

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