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THULin
Observer
Observer
468 Views
Registered: ‎12-13-2020

How to transplant a design with Synopsys IPs onto U280?

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We are trying to transplant our ASIC design onto U280.

The ASIC design uses some Synopsys IPs which cannot be synthesized in Vivado.

A common-used method is synthesizing by Synplify, but Synplify does not support Alveo U280.

Could you please give us some suggestions?

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yangc
Xilinx Employee
Xilinx Employee
423 Views
Registered: ‎02-27-2019

The ASIC design uses some Synopsys IPs which cannot be synthesized in Vivado.

Can you provide more details about it?From your description, It should be synthesized as RTL kernel, the output should be a .xo file. 

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yangc
Xilinx Employee
Xilinx Employee
424 Views
Registered: ‎02-27-2019

The ASIC design uses some Synopsys IPs which cannot be synthesized in Vivado.

Can you provide more details about it?From your description, It should be synthesized as RTL kernel, the output should be a .xo file. 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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THULin
Observer
Observer
401 Views
Registered: ‎12-13-2020

We just found that the latest version of Synplify can support U280, so this problem can be closed.

Thanks all the same.

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